LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 28

• Manufacturer Part Number: LCMXO2-1200ZE-1UWG25ITR50
• Description: FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1UWG25ITR50

• Rohs: yes
• Number Of Gates: 1200
• Embedded Block Ram - Ebr: 64 Kbit
• Number Of I/os: 19
• Maximum Operating Frequency: 400 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: WLCPS-25
• Distributed Ram: 10 Kbit
• Operating Supply Current: 56 uA

Table 2-12. Supported Input Standards
Types of Output Buffers
Differential Output Emulation
Capability
PCI Clamp Support
Single-Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI
SSTL18 (Class I, Class II)
SSTL25 (Class I, Class II)
HSTL18 (Class I, Class II)
Differential Interfaces
LVDS
BLVDS, MVDS, LVPECL, RSDS
Differential SSTL18 Class I, II
Differential SSTL25 Class I, II
Differential HSTL18 Class I, II
1. Bottom banks of MachXO2-640U, MachXO2-1200/U and higher density devices only.
2. Reduced functionality. Refer to TN1202,
1
No
Single-ended buffers with
complementary outputs (all I/O
banks)
All I/O banks
Input Standard
MachXO2-256,
MachXO2-640
MachXO2 sysIO Usage Guide
2-24
Single-ended buffers with
complementary outputs (all I/O
banks)
Differential buffers with true
LVDS outputs (50% on top
side)
All I/O banks
Clamp on bottom side only
3.3V









2
2
2
2
MachXO2-640U,
MachXO2-1200
2.5V










2
2
2
2
2
VCCIO (Typ.)
1.8V










2
2
2
2
2
for more detail.
MachXO2 Family Data Sheet
1.5






2
2
2
2
2
Single-ended buffers with
complementary outputs (all I/O
banks)
Differential buffers with true
LVDS outputs (50% on top
side)
All I/O banks
Clamp on bottom side only
1.2V
MachXO2-2000/U,

MachXO2-1200U

MachXO2-4000,
MachXO2-7000
2
Architecture