LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 73

• Manufacturer Part Number: LCMXO2-1200ZE-1UWG25ITR50
• Description: FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1UWG25ITR50

• Rohs: yes
• Number Of Gates: 1200
• Embedded Block Ram - Ebr: 64 Kbit
• Number Of I/os: 19
• Maximum Operating Frequency: 400 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: WLCPS-25
• Distributed Ram: 10 Kbit
• Operating Supply Current: 56 uA

Flash Download Time
JTAG Port Timing Specifications
f
t
t
t
t
t
t
t
t
t
t
t
t
MAX
BTCPH
BTCPL
BTS
BTH
BTCO
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
Symbol
t
1. Assumes sysMEM EBR initialized to an all zero pattern if they are used.
2. The Flash download time is measured starting from the maximum voltage of POR trip point.
REFRESH
Symbol
TCK clock frequency
TCK [BSCAN] clock pulse width low
TCK [BSCAN] setup time
TCK [BSCAN] hold time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
TCK [BSCAN] clock pulse width high
POR to Device I/O Active
1, 2
Parameter
Parameter
3-34
LCMXO2-256
LCMXO2-640
LCMXO2-640U
LCMXO2-1200
LCMXO2-1200U
LCMXO2-2000
LCMXO2-2000U
LCMXO2-4000
LCMXO2-7000
Device
DC and Switching Characteristics
MachXO2 Family Data Sheet
Typ.
Min.
0.6
1.0
1.9
1.9
1.4
1.4
2.4
2.4
3.8
20
20
10
20
—
—
—
—
—
—
—
8
8
Units
Max.
ms
ms
ms
ms
ms
ms
ms
ms
ms
25
10
10
10
25
25
25
—
—
—
—
—
—
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns