MAX5715AAUD+ Maxim Integrated, MAX5715AAUD+ Datasheet - Page 6

• Manufacturer Part Number: MAX5715AAUD+
• Description: Digital to Analog Converters - DAC 12Bit 4CH V Buff Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX5715AAUD+

• Rohs: yes
• Number Of Converters: 4
• Number Of Dac Outputs: 4
• Resolution: 12 bit
• Interface Type: SPI, Serial (3-Wire, Microwire)
• Settling Time: 4.5 us
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 797 mW
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage Buffered
• Supply Current: 1.16 mA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

ELECTRICAL CHARACTERISTICS (continued)
(V
values are at T
Maxim Integrated
Output DACs with Internal Reference and SPI Interface
Input Low Voltage (Note 11)
Input Leakage Current
Input Capacitance (Note 10)
DIgITAL OUTPUT (RDY)
Output High Voltage
Output Low Voltage
Output Short-Circuit Current
SPI TIMINg CHARACTERISTICS (CSB, SCLk, DIN, RDY)
SCLK Frequency
SCLK Period
SCLK Pulse Width High
SCLK Pulse Width Low
CSB Fall to SCLK Fall Setup Time
CSB Fall to SCLK Fall Hold Time
CSB Rise to SCLK Fall Hold Time
CSB Rise to SCLK Fall
SCLK Fall to CSB Fall
CSB Pulse Width High
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CLR Pulse Width Low
CLR Rise to CSB Fall
LDAC Pulse Width Low
LDAC Fall to SCLK Fall Hold
DD
= 2.7V to 5.5V, V
PARAMETER
A
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
= +25NC.) (Note 3)
DDIO
= 1.8V to 5.5V, V
SYMBOL
t
t
t
t
t
f
t
t
CSPW
CLPW
LDPW
I
t
t
t
V
SCLK
SCLK
CSS0
CSH0
CSH1
t
V
C
t
t
CSC
OSS
t
CSA
t
LDH
V
CSF
I
CH
DS
DH
CL
OH
IN
OL
IL
IN
GND
2.2V < V
1.8V < V
V
V
V
V
V
I
2.7V < V
daisy chain (Note 12)
1.8V < V
daisy chain (Note 12)
2.7V < V
1.8V < V
To first SCLK falling edge
Required for command to be executed
A
= 0V, C
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
Applies to the 24th SCLK falling edge
Applies to the 24th SCLK falling edge,
aborted sequence
Applies to 24th SCLK falling edge
SINK
IN
DDIO
DDIO
DDIO
DDIO
pplies to 24th SCLK falling edge,
= 0V or V
, I
> 2.5V, I
> 1.8V, I
> 2.5V, I
> 1.8V, I
SOURCE
MAX5713/MAX5714/MAX5715
L
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
= 200pF, R
DDIO
< 5.5V
< 2.2V
< 5.5V, standalone,
< 2.7V, standalone,
< 5.5V
< 2.7V
CONDITIONS
SOURCE
SOURCE
SINK
SINK
(Note 11)
L
= 3mA
= 2mA
= 2kI, T
= 3mA
= 2mA
A
= -40NC to +125NC, unless otherwise noted. Typical
V
V
- 0.2
- 0.2
MIN
100
DDIO
DDIO
4.5
20
30
12
20
20
20
20
20
0
0
0
0
8
8
8
0
0
5
±100
Q0.1
TYP
V
V
MAx
0.3 x
0.2 x
DDIO
DDIO
0.2
0.2
Q1
10
50
20
33
20
UNITS
MHz
mA
FA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V
6