MAX5715AAUD+ Maxim Integrated, MAX5715AAUD+ Datasheet - Page 16

• Manufacturer Part Number: MAX5715AAUD+
• Description: Digital to Analog Converters - DAC 12Bit 4CH V Buff Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX5715AAUD+

• Rohs: yes
• Number Of Converters: 4
• Number Of Dac Outputs: 4
• Resolution: 12 bit
• Interface Type: SPI, Serial (3-Wire, Microwire)
• Settling Time: 4.5 us
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 797 mW
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage Buffered
• Supply Current: 1.16 mA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

The MAX5713/MAX5714/MAX5715 feature an asynchro-
nous active-low CLR logic input that simultaneously sets
all four DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going SPI command. To allow a new SPI
command, drive CLR high, satisfying the t
requirement.
The MAX5713/MAX5714/MAX5715 feature a separate
supply pin (V
Connect V
The MAX5713/MAX5714/MAX5715 3-wire serial interface
is compatible with MICROWIRE, SPI, QSPI, and DSPs.
The interface provides three inputs, SCLK, CSB, and
DIN. The chip-select input (CSB, active low) frames the
data loaded through the serial data input (DIN). Following
a CSB input high-to-low transition, the data is shifted
in synchronously and latched into the input register on
each falling edge of the serial clock input (SCLK). Each
serial operation word is 24-bits long. The DAC data is
left justified as shown in Table 1. The serial input register
transfers its contents to the destination registers after
loading 24 bits of data on the 24th SCLK falling edge.
To initiate a new SPI operation, drive CSB high and then
low to begin the next operation sequence, being sure to
meet all relevant timing requirements. During CSB high
periods, SCLK is ignored, allowing communication to
other devices on the same bus. SPI operations consist-
Maxim Integrated
Table 1. Format DAC Data Bit Positions
Output DACs with Internal Reference and SPI Interface
MAX5713
MAX5714
MAX5715
PART
DDIO
DDIO
B15
D11
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
D7
D9
to the I/O supply of the host processor.
Interface Power Supply (V
) for the digital interface (1.8V to 5.5V).
B14
D10
D6
D8
B13
D5
D7
D9
SPI Serial Interface
Clear Input (CLR)
B12
D4
D6
D8
B11
D7
D3
D5
CSC
B10
D2
D4
D6
DDIO
MAX5713/MAX5714/MAX5715
timing
B9
D1
D3
D5
)
D2
D4
B8
D0
ing of more than 24 SCLK cycles are executed on the
24th SCLK falling edge, using the first three bytes of
data available. SPI operations consisting of less than 24
SCLK cycles will not be executed. The content of the SPI
operation consists of a command byte followed by a two
byte data word.
Figure 1 shows the timing diagram for the complete
3-wire serial interface transmission. The DAC code
settings (D) for the MAX5713/MAX5714/MAX5715 are
accepted in an offset binary format (see
Otherwise, the expected data format for each command
is listed in
cal SPI circuit application.
The elongated programming operation is typically used
for devices in daisy-chain applications. The RDY out-
put in the TSSOP version of the MAX5713/MAX5714/
MAX5715 feeds the CSB input of the next device in the
daisy-chain. The MAX5713/MAX5714/MAX5715 pulls the
RDY output low on the 24th SCLK falling edge, allowing
the next device in the chain to begin its SPI operation,
commencing with the 25th SCLK falling edge. See Figure
2 for timing characteristics of the elongated SPI program-
ming operation. In practice (t
will limit the daisy-chain SPI speed. Also in daisy-chain
applications, a partial write to the chain is possible
as long as the t
chooses not to program. See Figure 4 for an example of
a daisy-chain circuit application.
B7
D1
D3
x
Table
B6
D0
D2
x
CSA
2. See Figure 3 for an example of a typi-
D1
B5
x
x
SPI Daisy Chain/RDY Output
is met for the first device the user
B4
D0
x
x
(TSSOP Package Only)
CRF
B3
x
x
x
+ t
CSS0
B2
x
x
x
) requirements
B1
x
x
x
Table
B0
x
x
x
1).
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