XRT91L80ES Exar, XRT91L80ES Datasheet - Page 6

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PIN DESCRIPTIONS
SERIAL MICROPROCESSOR INTERFACE
HOST/HW
RESET
SCLK
N
SDO
SDI
INT
CS
AME
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVTTL,
LVTTL,
LVTTL,
LVTTL,
LVTTL,
L
EVEL
T
YPE
O
O
I
I
I
I
I
A10
C11
B10
P
C9
C8
B9
A9
IN
Host or Hardware Mode Select Input
The XRT91L80 offers two modes of operation for interfacing to the
device. The Host mode uses a serial microprocessor interface for
programming individual registers. The Hardware mode is controlled
by the state of the hardware pins set by the user. When left uncon-
nected, by default, the device is configured in the Hardware mode.
"Low" = Hardware Mode
"High" = Host Mode
This pin is provided with an internal pull-down.
Chip Select Input (Host Mode Only)
Active "Low" signal. This signal enables the serial microprocessor
interface by pulling chip select "Low". The serial microprocessor is
disabled when the chip select signal returns "High".
N
This pin is provided with an internal pull-up.
Serial Clock Input (Host Mode Only)
Once CS is pulled "Low", the serial microprocessor interface
requires 16 clock cycles for a complete Read or Write operation.
This pin is provided with an internal pull-down.
Serial Data Input (Host Mode Only)
When CS is pulled "Low", the serial data input is sampled on the ris-
ing edge of SCLK.
This pin is provided with an internal pull-down.
Serial Data Output (Host Mode Only)
If a Read function is initiated, the serial data output is updated on
the falling edge of SCLK8 through SCLK15, with the LSB (D0)
updated first. This enables the data to be sampled on the rising
edge of SCLK9 through SCLK16.
Interrupt Output (Host Mode Only)
Active "Low" signal. This signal is asserted "Low" when a change in
alarm status occurs. Once the status registers have been read, the
interrupt pin will return "High".
N
Master Reset Input
Active "Low" signal. When this pin is pulled "Low" for more than
10 S, the internal registers are set to their default state. See the
register description for the default values.
This pin is provided with an internal pull-up.
OTE
OTE
: The serial microprocessor interface does not support burst
: This pin requires an external pull-up resistor.
4
mode. Chip Select must be de-asserted after each
operation cycle.
D
ESCRIPTION
xr
xr
xr
xr
REV. 1.0.0