XRT91L80ES Exar, XRT91L80ES Datasheet - Page 10

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

TRANSMITTER SECTION
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
LOCKDET_CMU
FIFO_AUTORST
TXCLKO16DIS
TXCLKO16P
TXCLKO16N
OVERFLOW
FIFO_RST
N
AME
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVTTL,
LVTTL,
LVTTL,
L
LVDS
EVEL
T
YPE
O
O
O
I
I
I
M12
M13
N10
N13
N12
N11
P
N2
IN
Auxiliary Clock Output (155.52/166.63 MHz)
155.52/166.63 MHz auxiliary clock derived from CMU output.
This clock can also be used for the downstream device as a ref-
erence for generating the TXDI[3:0]P/N data and TXPCLKIP/N
clock input. This enables the downstream device and the STS-
48/STM-16 transceiver to be in synchronization. The output of
this pin is controlled by TXCLKO16DIS.
Auxiliary Clock Disable
This pin is used to control the activity of the auxiliary clock.
"Low" = TXCLKO16P/N Enabled
"High" = TXCLKO16P/N Disabled
This pin is provided with an internal pull-down.
CMU Lock Detect
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU Out of Lock
"High" = CMU Locked
Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
FIFO Control Reset
FIFO_RST should be held "High" for a minimum of 2 TXP-
CLKOP/N cycles after powering up and during manual FIFO
reset. After the FIFO_RST pin is returned "Low," it will take 8 to
10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an
interrupt indication that the FIFO has an overflow condition, this
pin is used to reset or flush out the FIFO.
"Low" = Normal Operation
"High" = Manual FIFO Reset
N
This pin is provided with an internal pull-down.
Automatic FIFO Overflow Reset
If this pin is set "High", the STS-48/STM-16 transceiver will
automatically flush the FIFO upon an overflow condition. Upon
power-up, the FIFO should be manually reset by setting
FIFO_RST "High" for a minimum of 2 TXPCLKOP/N cycles.
"Low" = Manual FIFO reset required for Overflow Conditions
"High" = Automatically resets FIFO upon Overflow Detection
This pin is provided with an internal pull-down.
OTE
8
: To automatically reset the FIFO, see FIFO_AUTORST
pin.
D
ESCRIPTION
xr
xr
xr
xr
REV. 1.0.0