XRT91L80ES Exar, XRT91L80ES Datasheet - Page 4

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
GENERAL DESCRIPTION .................................................................................................1
T
PIN DESCRIPTIONS ..........................................................................................................4
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................13
2.0 RECEIVE SECTION .............................................................................................................................14
3.0 TRANSMIT SECTION ..........................................................................................................................18
ABLE OF
APPLICATIONS ...........................................................................................................................................1
FEATURES
S
H
T
RECEIVER SECTION
P
N
JTAG ..........................................................................................................................................................12
ERIAL
RANSMITTER
OWER AND
PRODUCT ORDERING INFORMATION ..................................................................................................2
ARDWARE COMMON CONTROL
O
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 13
1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 13
1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
2.3 EXTERNAL SIGNAL DETECTION ................................................................................................................. 15
2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 16
2.5 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 16
2.6 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 17
2.7 PARALLEL RECEIVE DATA OUTPUT MUTE UPON LOSD ........................................................................ 17
2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE ......................................................................................... 17
2.9 RECEIVE PARALLEL DATA OUTPUT TIMING ............................................................................................ 17
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 18
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 19
3.3 TRANSMIT FIFO ............................................................................................................................................. 19
3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 20
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 20
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 21
3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 21
3.8 EXTERNAL LOOP FILTER ............................................................................................................................. 23
F
F
T
F
F
T
T
T
F
F
F
F
T
F
F
T
T
F
F
T
T
F
C
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
ABLE
IGURE
IGURE
ABLE
ABLE
IGURE
ONNECTS
M
1: R
2: D
3: C
4: LOSD D
5: R
6: T
7: T
8: C
9: L
ICROPROCESSOR INTERFACE
1. B
2. 196 BGA P
3. S
4. R
5. S
6. R
7. LVDS
8. R
9. T
10. T
11. T
12. S
13. L
C
......................................................................................................................................................2
ONTENTS
RANSMIT
RANSMIT
OOP TIMING AND REFERENCE DE
G
EFERENCE
IFFERENTIAL
LOCK AND
ECEIVE
LOCK
RANSMIT
LOCK
IMPLIFIED
ECEIVE
IMPLIFIED
ECEIVE
ECEIVE
S
ROUND
RANSMIT
RANSMIT
OOP
IMPLIFIED
.............................................................................................................................................11
ECTION
M
EXTERNAL BIASING RESISTORS
D
T
ECLARATION
.........................................................................................................................................9
P
ULTIPLIER
IMING
IAGRAM OF
S
P
P
P
P
ARALLEL
P
ERIAL
D
ARALLEL
ARALLEL
ARALLEL
ARALLEL
F
B
B
INOUT OF
P
FIFO
..................................................................................................................................10
ARALLEL
ATA
B
REQUENCY
LOCK
LOCK
CML I
ARALLEL
..................................................................................................................................6
LOCK
............................................................................................................
M
I
R
ODE
NPUT
AND
U
D
D
ECOVERY
D
NPUT
O
O
D
C
D
NIT
XRT91L80 ...................................................................................................................................... 1
P
ATA AND
IAGRAM OF
IAGRAM OF
I
THE XRT91L80 (T
UTPUT
UTPUT
ATA AND
LOCK
U
NPUT
IAGRAM OF
OLARITY
I
S
NPUT
......................................................................................................................5
I
SING AN
NTERFACE
P
YSTEM
O
S
ERFORMANCE
PTIONS
WING
O
I
NTERFACE
U
I
T
T
NTERFACE
C
UTPUT
IMING
NIT
IMING
S
C
TABLE OF CONTENTS
LOCK
I
............................................................................................................4
F
SIPO ........................................................................................................................... 16
-
NTERFACE
E
ETTING
LOCK
JITTER CONFIGURATIONS
P
PISO ......................................................................................................................... 20
ORWARD
XTERNAL
(N
P
ARAMETERS
B
ERFORMANCE
.............................................................................................................................. 17
.............................................................................................................................. 19
ON
T
LOCK
............................................................................................................................. 17
O
IMING
I
UTPUT
NPUT
B
-FEC
......................................................................................................................... 16
......................................................................................................................... 21
B
LOCK
OP
LOCK
..................................................................................................................... 14
E
.................................................................................................................... 20
C
S
RROR
V
T
LEANUP
AND
PECIFICATION
T
............................................................................................................... 18
IMING
IEW
.............................................................................................................. 14
IMING
............................................................................................................. 16
.......................................................................................................... 15
).......................................................................................................... 3
FEC M
C
ORRECTION
S
I
VCXO.......................................................................................... 22
S
PECIFICATION
PECIFICATIONS
.............................................................................................. 22
ODE
........................................................................................... 19
)...................................................................................... 13
.................................................................................... 13
............................................................................... 19
........................................................................... 17
xr
xr
xr
xr
REV. 1.0.0
I