XRT91L80ES Exar, XRT91L80ES Datasheet
XRT91L80ES
Specifications of XRT91L80ES
Related parts for XRT91L80ES
XRT91L80ES Summary of contents
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... SONET/SDH Test Equipment DWDM Termination Equipment PISO Re-Timer (Parallel Input Serial Output) CMU DLOOP RLOOPS SIPO (Serial Input CDR Parallel Output) Hardware Control • • (510) 668-7000 FAX (510) 668-7017 XRT91L80 REV. 1.0.0 LOCKDET_CDR, and TXOP/N RXIP/N LOSDMUTE PFD & Charge Pump • www.exar.com ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER FEATURES 2.488 / 2.666 Gbps Transceiver Targeted for SONET OC-48/SDH STM-16 Applications Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of 2.666 Gbps Single-chip fully integrated solution ...
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A AGND_RX TRST LOSDMUTE NC DGND B AGND_RX AGND_RX DGND NC SDEXT C RXIP AGND_RX AGND_RX POLARITY LOSDET D RXIN AGND_RX AVDD3.3_RX AVDD1.8_RX AVDD1.8_RX E AGND_RX AGND_RX AVDD3.3_RX AGND_RX TGND F XRES1N AGND_RX AVDD1.8_RX AGND_RX TGND G XRES1P AGND_RX AVDD1.8_RX ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ........................................................................................................................................... XRT91L80 ...................................................................................................................................... 1 IGURE LOCK IAGRAM OF ......................................................................................................................................................2 FEATURES PRODUCT ORDERING INFORMATION .................................................................................................. 196 BGA P THE XRT91L80 (T IGURE INOUT OF T ...
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REV. 1.0 IGURE IMPLIFIED IAGRAM OF THE 3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... IGURE RANSMIT ERIAL UTPUT 4.0 DIAGNOSTIC FEATURES ................................................................................................................... 24 4.1 SERIAL REMOTE LOOPBACK ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER PIN DESCRIPTIONS SERIAL MICROPROCESSOR INTERFACE AME EVEL YPE HOST/HW LVTTL, I LVCMOS CS LVTTL, I LVCMOS SCLK LVTTL, I LVCMOS SDI LVTTL, I LVCMOS SDO LVCMOS O INT LVCMOS O RESET ...
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REV. 1.0.0 HARDWARE COMMON CONTROL AME EVEL RLOOPS LVTTL, LVCMOS RLOOPP LVTTL, LVCMOS DLOOP LVTTL, LVCMOS 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER P YPE IN I C10 Serial Remote Loopback The serial remote loopback ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER HARDWARE COMMON CONTROL AME EVEL LOOPTM_JA LVTTL, LVCMOS LOOPTM_NOJA LVTTL, LVCMOS TRANSMITTER SECTION AME EVEL TXDI0P LVDS TXDI0N TXDI1P TXDI1N TXDI2P TXDI2N TXDI3P TXDI3N TXPCLKIP LVDS TXPCLKIN TXOP ...
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REV. 1.0.0 TRANSMITTER SECTION N L AME EVEL ALTFREQSEL LVTTL, LVCMOS VCXO_SEL LVTTL, LVCMOS VCXO_LOCK LVCMOS VCXO_LOCKEN LVTTL, LVCMOS CPOUT - LOOPBW LVTTL, LVCMOS TXPCLKOP LVDS TXPCLKON 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T P YPE IN ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TRANSMITTER SECTION AME EVEL TXCLKO16P LVDS TXCLKO16N TXCLKO16DIS LVTTL, LVCMOS LOCKDET_CMU LVCMOS OVERFLOW LVCMOS FIFO_RST LVTTL, LVCMOS FIFO_AUTORST LVTTL, LVCMOS P YPE IN O N10 Auxiliary Clock Output (155.52/166.63 MHz) N11 ...
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REV. 1.0.0 RECEIVER SECTION AME EVEL RXDO0P LVDS RXDO0N RXDO1P RXDO1N RXDO2P RXDO2N RXDO3P RXDO3N RXPCLKOP LVDS RXPCLKON DISRD LVTTL LVCMOS RXIP CMLDIFF RXIN XRES1P - XRES1N RXCLKO16P LVDS RXCLKO16N LOCKDET_CDR LVCMOS SDEXT ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER RECEIVER SECTION AME EVEL POLARITY LVTTL, LVCMOS LOSDET LVCMOS LOSDMUTE LVTTL, LVCMOS POWER AND GROUND AME YPE VDD3.3 PWR A8, D9, D10, D11, E11, P13, P14 AVDD3.3_RX PWR ...
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REV. 1.0.0 POWER AND GROUND N T AME YPE AVDD1.8_TX PWR J1, J4, L6, L7, L8, M3, N9, DGND GND A5, A12, B3, B8, B12, F11, F12, G11, G12, G13, G14, H11, H12, J11, J12, K12, ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JTAG IGNAL AME IN YPE TCK N3 I TMS N1 I TDI M8 I TDO B11 O TRST ESCRIPTION Test clock: Boundary Scan Clock Input. Test ...
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REV. 1.0.0 1.0 FUNCTIONAL DESCRIPTION The XRT91L80 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high- speed serial interface to optical networks. The transceiver converts 4-bit parallel data at 622.08/666.51 Mbps ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.0 RECEIVE SECTION The receive section of XRT91L80 includes the differential inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter (SIPO). The receiver accepts the high speed Non- ...
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REV. 1.0.0 2.2 Receive Clock and Data Recovery The clock and data recovery unit accepts the high speed NRZ serial data from the differential CML receiver and generates a clock that is the same frequency as ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T ABLE SDEXT POLARITY LOSDMUTE 2.4 Receive Serial Input to Parallel Output (SIPO) The SIPO is used to convert the 2.488/2.666 ...
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REV. 1.0.0 2.6 Receive Parallel Interface LVDS Operation When operating the 4-bit Differential bus in LVDS mode, a 402 and XRES1N to properly bias the RXDO[3:0]P/N and RXPCLKOP/N pins. Figure 7 shows the proper biasing resistor ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at ...
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REV. 1.0.0 4.3 Digital Local Loopback The digital local loopback is activated when the DLOOP signal is set "High." When digital local loopback is activated, the high-speed data from the output of the parallel to serial ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.4 SONET Jitter Requirements SONET equipment jitter requirements are specified for the following three types of jitter. The definitions of each of these types of jitter are given below. SONET equipment jitter requirements are ...
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REV. 1.0.0 F 20. 91L80 M IGURE EASURED JITTER TOLERANCE WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING 2.488 G STS-48. AT BPS IN F 21. 91L80 M IGURE EASURED JITTER TOLERANCE WITHOUT JITTER ATTENUATION IN REMOTE ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER F 22. 91L80 M IGURE EASURED JITTER TRANSFER WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT 2.488 G STS-48. BPS 23. M IGURE EASURED JITTER TRANSFER WITHOUT JITTER ATTENUATION IN REMOTE ...
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REV. 1.0.0 4.4.3 Jitter Generation Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The Bellcore and ITU requirement for this type jitter is 0.01UI ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.0 TRANSMIT SECTION The transmit section of the XRT91L80 accepts 4-bit parallel LVDS data and converts it to serial CML data output intented to interface to an optical module. It consists of a 4-bit ...
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REV. 1.0.0 3.2 Transmit Parallel Data Input Timing When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 10 and Table ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER device will set the OVERFLOW pin to a "High" level and will automatically reset and center the FIFO. Figure 11 provides a detailed overview of the transmit FIFO in a system interface. F 11. ...
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REV. 1.0.0 3.6 Clock Multiplier Unit (CMU) and Re-Timer The high-speed serial clock synthesized by the CMU is divided by 4, and is presented to the upstream device as TXPCLKOP/N clock . The upstream device should ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER The on-chip phase/frequency detector can also be used to remove the jitter from a noisy reference signal that is applied to the REFCLKP/N inputs. In this case, the LOOPTM_NOJA pin should be set "Low", ...
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REV. 1.0.0 3.8 External Loop Filter As shown in Figure 13, there is an internal charge pump used to drive an external loop filter and external VCXO. The charge pump current is fixed at 250uA. Figure ...
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REV. 1.0.0 5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the transceiver. Optional pins such as SDO, INT, and RESET allow the ability ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 5.2 16 ERIAL ATA NPUT ESCRITPTION The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is updated on the ...
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REV. 1.0.0 6.0 REGISTER MAP AND BIT DESCRIPTIONS T ABLE R ADDR YPE Channel 0 Control Register (0x00h - 0x05h) 0 0x00 R/W Reserved Reserved 1 0x01 RUR Reserved Reserved 2 0x02 RO ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 12: M ABLE I NTERRUPT AME D7 Reserved This Register Bit is Not Used D6 Reserved This Register Bit is Not Used D5 Reserved This Register Bit is Not Used ...
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REV. 1.0 AME D5 Reserved This Register Bit is Not Used D4 VCXOD Voltage Controlled External Oscillator Lock Detection The VCXOD is used to indicate whether the internal clock refer- ence is locked ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER T 14: M ABLE AME D4 LOOPBW CMU Loop Band Width Select This bit is used to select the bandwidth of the clock multiplier unit of the transmit path to ...
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REV. 1.0.0 T 15: M ABLE AME D7 Reserved This Register Bit is Not Used D6 POLARITY Polarity for SDEXT Input Controls the Signal Detect polarity convention of SDEXT. "0" = SDEXT ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER AME D5 Reserved This Register Bit is Not Used D4 Reserved This Register Bit is Not Used D3 Reserved This Register Bit is Not Used D2 DLOOP Digital Local Loopback Digital ...
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REV. 1.0.0 T 17: M ABLE AME D7 Device "ID" The device "ID" of the XRT91L80 LIU is 0xC0h. Along with the revision "ID", the device "ID" is used to enable software to ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 7.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Thermal Resistance of STBGA Package.... Thermal Resistance of STBGA Package.... ESD Protection (HBM)..........................................>2000V ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS S T YMBOL YPE VDD 1.8V Digital Core Power ...
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REV. 1.0.0 POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS S T YMBOL YPE AVDD Analog Transmit I/O Power Supply Voltage 3.3_TX (AVDD3.3_TX) AVDD Analog Receive I/O Power Supply Voltage 3.3_RX (AVDD3.3_RX) I 1.8V Total Power Supply Current ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD = 1.8V + 5%, VDD 1 YMBOL YPE ARAMETER V LVDS Output High Voltage OH V LVDS Output Low Voltage OL V ...
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REV. 1.0 ART UMBER XRT91L80IB 196 Shrink Thin Ball Grid Array (12 12.0 mm, STBGA) D Seating Plane A2 A1 SYMBOL 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH ...
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XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER REVISION HISTORY EVISION ATE P1.0.0 October 2004 1st release of the XRT91L80 product brief P1.0.1 October 2004 Fixed typos throughout document P1.0.2 October 2004 Fixed typos throughout document P1.0.3 January 2005 ...
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... Changed I acteristics EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...