XRT91L80ES Exar, XRT91L80ES Datasheet - Page 11
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XRT91L80ES
Manufacturer Part Number
XRT91L80ES
Description
Bus Transceivers Transceiver
Manufacturer
Exar
Datasheet
1.XRT91L80ES.pdf
(46 pages)
Specifications of XRT91L80ES
Product Category
Bus Transceivers
Rohs
yes
xr
xr
xr
xr
REV. 1.0.0
RECEIVER SECTION
LOCKDET_CDR
RXCLKO16P
RXCLKO16N
RXPCLKOP
RXPCLKON
XRES1P
XRES1N
RXDO0P
RXDO0N
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
SDEXT
DISRD
N
RXIP
RXIN
AME
CMLDIFF
LVCMOS
LVCMOS
LVCMOS
LVTTL,
LVTTL
L
LVDS
LVDS
LVDS
EVEL
-
T
YPE
O
O
O
O
I
I
I
I
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
E13
F13
C14
D14
C13
D13
A14
B14
E14
F14
C12
P
G1
C1
D1
F1
A6
A7
C7
B5
IN
Receive Parallel Data Output
622Mbps 4-bit parallel receive data output is updated simulta-
neously on the rising edge of the RXPCLKOP/N output. The 4-
bit parallel interface is de-multiplexed from the receive serial
data input MSB first (RXDO3P/N).
N
Receive Parallel Clock Output
622.08 MHz parallel clock output used to update the 4-bit paral-
lel receive data output RXDO[3:0]P/N at the rising edge of this
clock..
N
Parallel Receive Data Output Disable
This pin is used to disable the RXDO[3:0]P/N parallel receive
data output bus asynchronously.
"Low" = Normal Mode
"High" = Forces RXDO[3:0]P/N to a logic state "0"
This pin is provided with an internal pull-down.
Receive Serial Data Input
The receive serial data stream of 2.488 Gbps is applied to
these input pins. In Forward Error Correction, the receive
serial data stream is 2.666 Gbps.
External LVDS Biasing Resistors
A 402 resistor with +/-1% tolerance should be placed across
these 2 pins for proper biasing.
Auxiliary Clock Output (155.52/166.63 MHz)
155.52/166.63 MHz auxiliary clock derived from divide-by-16
CDR recovered clock.
CDR Lock Detect
This pin is used to monitor the lock condition of the clock and
data recovery unit.
"Low" = CDR Out of Lock
"High" = CDR Locked
Signal Detect Input from Optical Module
Hardware Mode When inactive, it will immediately declare a
Loss of Signal Detect (LOSD) condition and assert LOSDET
output pin and control the activity of the RXDO[3:0]P/N parallel
data output based on LOSDMUTE pin setting.
Host Mode In addition to asserting LOSDET output pin, it will
update the LOSD condition on the registers and control the
activity of the RXDO[3:0]P/N parallel data output based on
LOSDMUTE register bit setting.
"Active" = Normal Operation
"Inactive" = LOSD Condition (SDEXT detects signal absence)
This pin is provided with an internal pull-down.
OTE
OTE
9
: The XRT91L80 can output 666.51 Mbps 4-bit parallel
: The XRT91L80 can output a 666.51 MHz receive clock
receive data output for Forward Error Correction (FEC)
Applications.
output for Forward Error Correction (FEC).
D
ESCRIPTION
XRT91L80