LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 255

• Manufacturer Part Number: LPC1111FHN33/102'5
• Description: ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1111FHN33/102'5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1111
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Program Memory Type: Flash
• Factory Pack Quantity: 4000

NXP Semiconductors
Table 236. Master Receiver mode
UM10398
User manual
Status
Code
(STAT)
0x08
0x10
0x38
0x40
0x48
0x50
0x58
Status of the I
and hardware
A START condition
has been transmitted.
A Repeated START
condition has been
transmitted.
Arbitration lost in NOT
ACK bit.
SLA+R has been
transmitted; ACK has
been received.
SLA+R has been
transmitted; NOT ACK
has been received.
Data byte has been
received; ACK has
been returned.
Data byte has been
received; NOT ACK
has been returned.
2
C-bus
Application software response
To/From DAT
Load SLA+R
Load SLA+R or
Load SLA+W
No DAT action or
No DAT action
No DAT action or
No DAT action
No DAT action or
No DAT action or
No DAT action
Read data byte or 0
Read data byte
Read data byte or 1
Read data byte or 0
Read data byte
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
To CON
STA STO SI
X
X
X
0
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
0
1
X
X
X
0
1
X
X
X
Next action taken by I
SLA+R will be transmitted; ACK bit will be
received.
As above.
SLA+W will be transmitted; the I
will be switched to MST/TRX mode.
I
enter slave mode.
A START condition will be transmitted
when the bus becomes free.
Data byte will be received; NOT ACK bit
will be returned.
Data byte will be received; ACK bit will be
returned.
Repeated START condition will be
transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be received; NOT ACK bit
will be returned.
Data byte will be received; ACK bit will be
returned.
Repeated START condition will be
transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
2
C-bus will be released; the I
UM10398
© NXP B.V. 2012. All rights reserved.
2
C hardware
2
C block will
2
255 of 538
C block