LPC1112FHN33/202 NXP Semiconductors, LPC1112FHN33/202 Datasheet - Page 54

• Manufacturer Part Number: LPC1112FHN33/202
• Description: ARM Microcontrollers - MCU CortexM0 32bit 16KB
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/202

• Rohs: yes
• Core: ARM Cortex M0
• Data Bus Width: 32 bit

NXP Semiconductors
LPC111X
Product data sheet
CAUTION
7.17.5 APB interface
7.17.6 AHBLite
7.17.7 External interrupt inputs
7.18 Emulation and debugging
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC111x user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 20 February 2013
Section
LPC1110/11/12/13/14/15
7.17.1).
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2013. All rights reserved.
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