LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 54

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
4.3.2 General purpose registers 0 to 3
4.3.3 General purpose register 4
Table 49.
The general purpose registers retain data through the Deep power-down mode when
power is still applied to the V
Only a “cold” boot when all power has been completely removed from the chip will reset
the general purpose registers.
Table 50.
The general purpose register 4 retains data through the Deep power-down mode when
power is still applied to the V
Only a “cold” boot, when all power has been completely removed from the chip, will reset
the general purpose registers.
Remark: If there is a possibility that the external voltage applied on pin V
2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be
disabled in this register before entering Deep power-down mode in order for the chip to
wake up.
Table 51.
Bit
8
10:9
11
31:12
Bit
31:0
Bit
9:0
Symbol
SLEEPFLAG
-
DPDFLAG
-
Symbol
-
Symbol
GPDATA
Power control register (PCON, address 0x4003 8000) bit description
General purpose registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to
0x4003 8010) bit description
General purpose register 4 (GPREG4, address 0x4003 8014) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Value
0
1
-
0
1
-
Value
-
Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU)
Description
Data retained during Deep power-down mode.
DD
DD
Description
Sleep mode flag
Read: No power-down mode entered.
LPC111x/LPC11Cxx is in Active mode.
Write: No effect.
Read: Sleep/Deep-sleep or Deep power-down mode
entered.
Write: Writing a 1 clears the SLEEPFLAG bit to 0.
Reserved. Do not write ones to this bit.
Deep power-down flag
Read: Deep power-down mode not entered.
Write: No effect.
Read: Deep power-down mode entered.
Write: Clear the Deep power-down flag.
Reserved. Do not write ones to this bit.
pin but the chip has entered Deep power-down mode.
pin but the chip has entered Deep power-down mode.
Description
Reserved. Do not write ones to this bit.
UM10398
© NXP B.V. 2012. All rights reserved.
DD
drops below
…continued
Reset
value
0x0
54 of 538
Reset
value
0
0x0
0x0
0x0
0x0
0x0
Reset
value
0x0