LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 369

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
21.4 Applications
21.5 Description
21.6 Pin description
Table 326. Counter/timer pin description
21.7 Register description
UM10398
User manual
Pin
CT32B0_CAP[1:0]
CT32B1_CAP[1:0]
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. The peripheral clock is provided by
the system clock (see
trap the timer value when an input signal transitions, optionally generating an interrupt.
In PWM mode, three match registers can be used to provide a single-edge controlled
PWM output on the match output pins. One match register is used to control the PWM
cycle length.
Remark: 32-bit counter/timer0 (CT32B0) and 32-bit counter/timer1 (CT32B1) are
functionally identical except for the peripheral base address.
Table 326
32-bit counter/timer0 contains the registers shown in
contains the registers shown in
Type
Input
Output
•
•
•
•
Interval timer for counting internal events
Pulse Width Demodulator via capture input
Free running timer
Pulse Width Modulator via match outputs
gives a brief summary of each of the counter/timer related pins.
Description
Capture Signals:
A transition on a capture pin can be configured to load one of the Capture Registers
with the value in the Timer Counter and optionally generate an interrupt.
The counter/timer block can select a capture signal as a clock source instead of the
PCLK derived clock. For more details see
(TMR32B0CTCR and TMR32B1TCR)” on page
External Match Output of CT32B0/1:
When a match register TMR32B0/1MR3:0 equals the timer counter (TC), this output
can either toggle, go LOW, go HIGH, or do nothing. The External Match Register
(EMR) and the PWM Control register (PWMCON) control the functionality of this
output.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Figure
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
8). Each counter/timer also includes one capture input to
Table
328. More detailed descriptions follow.
Section 21.7.11 “Count Control Register
Table 327
378.
and 32-bit counter/timer1
UM10398
© NXP B.V. 2012. All rights reserved.
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