LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 224

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
14.7 Functional description
UM10398
User manual
14.6.9 SPI/SSP Interrupt Clear Register
14.7.1 Texas Instruments synchronous serial frame format
Table 215: SPI/SSP Masked Interrupt Status register (SSP0MIS - address 0x4004 001C,
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SPI controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO or disabled by
clearing the corresponding bit in SSPIMSC registers.
Table 216: SPI/SSP interrupt Clear Register (SSP0ICR - address 0x4004 0020, SSP1ICR -
Figure 36
by the SPI module.
Bit
0
1
2
3
31:4
Bit
0
1
31:2
Symbol
RORMIS
RTMIS
RXMIS
TXMIS
-
Symbol
RORIC
RTIC
-
shows the 4-wire Texas Instruments synchronous serial frame format supported
SSP1MIS - address 0x4005 801C) bit description
address 0x4005 8020) bit description
All information provided in this document is subject to legal disclaimers.
This bit is 1 if the Rx FIFO is at least half full, and this interrupt
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
This bit is 1 if the Rx FIFO is not empty, has not been read for
a time-out period, and this interrupt is enabled. The time-out
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
 [SCR+1]).
is enabled.
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
Writing a 1 to this bit clears the Rx FIFO was not empty and
has not been read for a timeout period interrupt. The timeout
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
 [SCR+1]).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 12 — 24 September 2012
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
UM10398
© NXP B.V. 2012. All rights reserved.
Reset Value
0
0
0
0
NA
Reset Value
NA
NA
NA
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