LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 233
LPC1112FHN33/203,5
Manufacturer Part Number
LPC1112FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1112FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1112
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
16 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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NXP Semiconductors
15.5 General description
UM10398
User manual
15.5.1 I
A typical I
direction bit (R/W), two types of data transfers are possible on the I
The I
master receiver mode, slave transmitter mode and slave receiver mode.
The I
power off to the ARM Cortex-M0 without interfering with other devices on the same
I
Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I
products which NXP Semiconductors is now providing.
2
2
Fig 44. I
•
•
C-bus.
C Fast-mode Plus
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START condition. Since a Repeated
START condition is also the beginning of the next serial transfer, the I
be released.
2
2
C interface is byte oriented and has four operating modes: master transmitter mode,
C interface complies with the entire I
I
2
C bus
2
2
C-bus configuration is shown in
C-bus configuration
SDA
All information provided in this document is subject to legal disclaimers.
LPC11xx
Rev. 12 — 24 September 2012
SCL
pull-up
resistor
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
OTHER DEVICE WITH
I
2
C INTERFACE
2
Figure
C specification, supporting the ability to turn
pull-up
resistor
44. Depending on the state of the
OTHER DEVICE WITH
I
2
C INTERFACE
2
C-bus:
UM10398
© NXP B.V. 2012. All rights reserved.
2
C bus will not
2
SDA
SCL
C-bus
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