LPC1113FHN33/203,5 NXP Semiconductors, LPC1113FHN33/203,5 Datasheet - Page 355

• Manufacturer Part Number: LPC1113FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
20.5 Description
20.6 Pin description
Table 310. Counter/timer pin description
20.7 Register description
Table 311. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000)
UM10398
User manual
Pin
CT32B0_CAP0
CT32B1_CAP0
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
Name
TMR32B0IR
TMR32B0TCR
TMR32B0TC
TMR32B0PR
Access Address
R/W
R/W
R/W
R/W
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. The peripheral clock is provided by
the system clock (see
trap the timer value when an input signal transitions, optionally generating an interrupt.
In PWM mode, three match registers can be used to provide a single-edge controlled
PWM output on the match output pins. One match register is used to control the PWM
cycle length.
Remark: 32-bit counter/timer0 (CT32B0) and 32-bit counter/timer1 (CT32B1) are
functionally identical except for the peripheral base address.
Table 310
32-bit counter/timer0 contains the registers shown in
contains the registers shown in
Type
Input
Output
offset
0x000
0x004
0x008
0x00C
gives a brief summary of each of the counter/timer related pins.
Description
Capture Signals:
A transition on a capture pin can be configured to load one of the Capture Registers
with the value in the Timer Counter and optionally generate an interrupt.
The counter/timer block can select a capture signal as a clock source instead of the
PCLK derived clock. For more details see
(TMR32B0CTCR and TMR32B1TCR)” on page
External Match Output of CT32B0/1:
When a match register TMR32B0/1MR3:0 equals the timer counter (TC), this output
can either toggle, go LOW, go HIGH, or do nothing. The External Match Register
(EMR) and the PWM Control register (PWMCON) control the functionality of this
output.
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
Description
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Figure
8). Each counter/timer also includes one capture input to
Table
312. More detailed descriptions follow.
Section 20.7.11 “Count Control Register
Table 311
363.
and 32-bit counter/timer1
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0
0
0
0
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