LPC1113FHN33/203,5 NXP Semiconductors, LPC1113FHN33/203,5 Datasheet - Page 300

• Manufacturer Part Number: LPC1113FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.7.2.4.3 Loop-back mode combined with Silent mode
16.7.2.4.4 Basic mode
This mode is provided for self-test functions. To be independent from external stimulation,
the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot
of a data/remote frame) in Loop-back mode. In this mode the CAN core performs an
internal feedback from its CAN_TXD output to its CAN_RXD input. The actual value of the
CAN_RXD input pin is disregarded by the CAN Core. The transmitted messages can be
monitored at the CAN_TXD pin.
It is also possible to combine Loop-back mode and Silent mode by programming bits
LBACK and SILENT to one at the same time. This mode can be used for a “Hot Selftest”,
meaning the C_CAN can be tested without affecting a running CAN system connected to
the pins CAN_TXD and CAN_RXD. In this mode the CAN_RXD pin is disconnected from
the CAN Core and the CAN_TXD pin is held recessive.
The CAN Core can be set in Basic mode by programming the Test Register bit BASIC to
one. In this mode the CAN controller runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the
IF1 Registers is requested by writing the BUSY bit of the IF1 Command Request Register
to ‘1’. The IF1 Registers are locked while the BUSY bit is set. The BUSY bit indicates that
the transmission is pending.
Fig 62. CAN core in Loop-back mode
Fig 63. CAN core in Loop-back mode combined with Silent mode
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
C_CAN
C_CAN
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
CAN_TXD CAN_RXD
CAN_TXD CAN_RXD
= 1
Rx
Rx
CAN CORE
CAN CORE
Tx
Tx
UM10398
© NXP B.V. 2012. All rights reserved.
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