LPC1113FHN33/203,5 NXP Semiconductors, LPC1113FHN33/203,5 Datasheet - Page 217

• Manufacturer Part Number: LPC1113FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

14.1 How to read this chapter
14.2 Basic configuration
14.3 Features
14.4 General description
UM10398
User manual
The SPI blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The
second SPI block, SPI1, is available on LQFP48 packages.
For parts in the LPC1100 and LPC1100L series, SPI1 is not available on HVQFN33
packages.
For parts in the LPC1100XL series, SPI1 is supported on all packages.
Remark: Both SPI blocks include the full SSP feature set, and all register names use the
SSP prefix.
The SPI0/1 are configured using the following registers:
The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
1. Pins: The SPI pins must be configured in the IOCONFIG register block. In addition,
2. Power: In the SYSAHBCLKCTRL register, set bit 11 and bit 18
3. Peripheral clock: Enable the SPI0/1 peripheral clock by writing to the SSP0/1CLKDIV
4. Reset: Before accessing the SPI blocks, ensure that the SSP_RST_N bits (bit 0 and
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UM10398
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
Rev. 12 — 24 September 2012
use the IOCON_LOC register (see
function.
registers
bit 2) in the PRESETCTRL register
signal to the SPI blocks.
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
Synchronous Serial Communication.
Supports master or slave operation.
Eight-frame FIFOs for both transmit and receive.
4-bit to 16-bit frame.
(Section 3.5.15
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
and
Section
Section
(Table
3.5.17).
9) is set to 1. This de-asserts the reset
7.4) to select a location for the SCK0
(Table
© NXP B.V. 2012. All rights reserved.
21).
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