MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 96
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Note:
Table 117. PWM Scale B Register (PWMSCLB)
Functional Description and Application Information
4.13.3.5
Each channel has a dedicated 8-bit up/down counter, which runs at the rate of the selected clock source. The counter can be
read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts
from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period
register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of
both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is
also cleared at the end of the effective period (see
Aligned Outputs"”
a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more
detailed information on the operation of the counters, see
Table 118. PWM Channel Counter Registers (PWMCNTx)
Freescale Semiconductor
Note:
Offset
91.
Reset
Offset
90.
Reset
W
R
W
R
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(91)
(90)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
0x64/0x65
0x63
Bit 7
Bit 7
0
0
7
PWM Channel Counter Registers (PWMCNTx)
0
7
Writing to the counter while the channel is enabled can cause an irregular PWM cycle to
occur.
for more details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When
0
0
6
6
0
6
6
5
0
0
5
0
5
5
Section 4.13.4.2.5, “Left Aligned Outputs"”
Section 4.13.4.2.4, “PWM Timer
NOTE
4
0
0
4
0
4
4
0
0
3
3
0
3
3
0
0
2
2
2
0
2
Counters"”.
PWM Control Module (PWM8B2C)
and
Section 4.13.4.2.6, “Center
0
0
1
1
1
0
1
Access: User read/write
Access: User read/write
MM912F634
Bit 0
Bit 0
0
0
0
0
0
96
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