MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 220
MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Table 272. Debug Trace Buffer Register (DBGTB)
Functional Description and Application Information
4.31.3.2.4
Table 269. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 270. DBGC2 Field Descriptions
4.31.3.2.5
Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set.
Freescale Semiconductor
Address:
Address: 0x0023
Resets
Other
Reset
ABCM[1:0]
POR
W
W
R
R
Field
1–0
Table 271. ABCM Encoding
Note:
181.
0x0024, 0x0025
ABCM
Bit 15
—
00
01
10
11
15
X
Currently defaults to Comparator A, Comparator B disabled.
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in
Table
0
0
7
Table 268. TRCMOD Trace Mode Bit Encoding (continued)
Debug Control Register2 (DBGC2)
Debug Trace Buffer Register (DBGTBH:DBGTBL)
Bit 14
—
14
271.
X
TRCMOD
Bit 13
01
10
11
—
13
X
0
0
6
Bit 12
Match0 mapped to comparator A match: Match1 mapped to comparator B match.
—
12
X
Match 0 mapped to comparator A/B outside range: Match1 disabled.
Bit 11
Match 0 mapped to comparator A/B inside range: Match1 disabled.
—
11
X
5
0
0
Bit 10
—
10
X
Bit 9
—
X
9
0
0
4
Bit 8
—
Reserved
X
8
Description
Description
Description
Pure PC
Loop1
Detail
Bit 7
—
X
7
(181)
0
0
3
Bit 6
—
X
6
Bit 5
—
X
5
S12S Debug (S12SDBGV1) Module
0
0
2
Bit 4
—
X
4
Bit 3
—
X
3
1
0
Bit 2
—
X
2
ABCM
Bit 1
MM912F634
—
X
1
0
0
Bit 0
—
X
0
220
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