MM912F634DV1AER2 Freescale Semiconductor, MM912F634DV1AER2 Datasheet - Page 196
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MM912F634DV1AER2
Manufacturer Part Number
MM912F634DV1AER2
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AER2
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
4.5 V
Supply Voltage - Min
4.5 V
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Functional Description and Application Information
4.30.1.2.2
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure
operation prevents access to Flash or EEPROM other than allowing erasure. For more information please see
“Security"”.
4.30.1.2.3
The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM firmware commands as well as the
hardware BACKGROUND command cannot be used and are ignored. In this case the CPU can not enter BDM active mode, and
only hardware read and write commands are available. Also the CPU can not enter a low power mode (stop or wait) during BDM
active mode.
In stop mode, the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the BDM clocks will restart
and BDM will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The
BDM is now ready to receive a new command.
4.30.1.3
A block diagram of the BDM is shown in
Freescale Semiconductor
System
Host
Block Diagram
Register Block
Secure Mode Operation
Low Power Modes
BKGD
BDMACT
ENBDM
UNSEC
TRACE
BDMSTS
Register
SDV
Interface
Serial
Figure
Control
Data
Figure 59. BDM Block Diagram
59.
Standard BDM Firmware
16-Bit Shift Register
Secured BDM Firmware
Instruction Code
LOOKUP TABLE
LOOKUP TABLE
Execution
and
Background Debug Module (S12SBDMV1)
Bus Interface
Control Logic
and
Section 4.30.4.1,
Address
Data
Control
Clocks
MM912F634
196
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