C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 261
C8051F961-A-GM
Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F961-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
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SFR Definition 19.2. PCLKEN: Peripheral Clock Enable
SFR Page = 0xF; SFR Address = 0xFE
Name
Reset
Bit
7:4
Type
3
2
1
0
Bit
PCLKEN3 Clock Enable Controls for Peripherals in Low Power Idle Mode.
PCLKEN2 Clock Enable Controls for Peripherals in Low Power Idle Mode.
PCLKEN1 Clock Enable Controls for Peripherals in Low Power Idle Mode.
PCLKEN0 Clock Enable Controls for Peripherals in Low Power Idle Mode.
Unused
Name
R/W
7
Read = 0b; Write = don’t care.
0: Disable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Idle
Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Idle
Mode.
0: Disable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Idle Mode.
1: Enable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Idle Mode.
0: Disableclocks to ADC0 and PCA0 in Low Power Idle Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Idle Mode.
0: Disable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
1: Enable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
R/W
6
R/W
5
R/W
Rev. 0.5
4
Function
3
2
PCLKEN[3:0]
R/W
C8051F96x
1
0
261
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