C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 339
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C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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Price
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Part Number:
C8051F960-A-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
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26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode)
In Contrast Control Mode 2, a minimum contrast voltage is maintained, as shown in Figure 26.4. The
VLCD supply is powered directly from VBAT as long as VBAT is higher than the programmable VBAT mon-
itor threshold voltage. As soon as the VBAT supply monitor detects that VBAT has dropped below the pro-
grammed value, the charge pump will be automatically enabled in order to acheive the desired minimum
contrast voltage on VLCD. Minimum Contrast Mode is selected using the following procedure:
26.3.3. Contrast Control Mode 3 (Constant Contrast Mode)
In Contrast Control Mode 3, a constant contrast voltage is maintained. The VLCD supply is regulated to the
programmed contrast voltage using a variable resistor between VBAT and VLCD as long as VBAT is
higher than the programmable VBAT monitor threshold voltage. As soon as the VBAT supply monitor
detects that VBAT has dropped below the programmed value, the charge pump will be automatically
enabled in order to acheive the desired contrast voltage on VLCD. Constant Contrast Mode is selected
using the following procedure:
1. Clear Bit 2 of the LCD0MSCN register to 0b (LCD0MSCN &= ~0x04)
2. Set Bit 0 of the LCD0MSCF register to 1b (LCD0MSCF |= 0x01)
3. Set Bit 3 of the LCD0PWR register to 1b (LCD0PWR |= 0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
1. Set Bit 2 of the LCD0MSCN register to 1b (LCD0MSCN |= 0x04)
2. Clear Bit 0 of the LCD0MSCF register to 0b (LCD0MSCF &= ~0x01)
3. Set Bit 3 of the LCD0PWR register to 1b (LCD0PWR |= 0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
V B A T
V L C D
V B A T
V L C D
Figure 26.4. Contrast Control Mode 2
Figure 26.5. Contrast Control Mode 3
Rev. 0.5
C8051F96x
339
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