C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 199
![no-image](/images/no-image-200.jpg)
C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F960-A-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F960-A-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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14.6.5.1. CTR Data Flow
The AES0 module data flow for CTR encryption and decryption shown in Figure 14.5. The data flow is the
same for encryption and decryption. The AES0DCF sfr is always configured to XOR AES0XIN with the
AES Core output.The XOR on the input is not used. The AES core is configured for an encryption opera-
tion. The encryption key is written to AES0KIN. The key size is set to the desired key size.
For an encryption operation, the plaintext is written to the AES0BIN sfr and the ciphertext is read from
AES0YOUT. For decryption, the ciphertext is written to AES0BIN and the plaintext is read from
AES0YOUT.
Note the counter must be incremented after each block using software.
AES0DCFG
AES0BCFG
AES0KIN
internal state
machine
Figure 14.8. Counter Mode Data Flow
Key
In
Rev. 0.5
AES0BIN
Data Out
Data In
Core
AES
AES0YOUT
+
+
Key
Out
AES0XIN
C8051F96x
199
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