C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 127
C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
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SFR Definition 9.1. PSBANK: Program Space Bank Select
SFR Page = All Pages; SFR Address = 0x84
9.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F96x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can be
re-configured to write and erase on-chip flash memory space. MOVC instructions are always used to read
flash memory, while MOVX write instructions are used to erase and write flash. This flash access feature
provides a mechanism for the C8051F96x to update program code and use the program memory space for
non-volatile data storage. Refer to Section “18. Flash Memory” on page 244 for further details.
9.2. Data Memory
The C8051F96x device family includes 8448 bytes (C8051F960/1/2/3/4/5/6/7) or 4352 bytes
(C8051F968/9) of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space of
the 8051. 8192 or 4096 bytes of this memory is on-chip “external” memory. The data memory map is
shown in Figure 9.1 for reference.
Note:
Name
Reset
Bit
7:6
5:4 COBANK[1:0] Constant Operations Bank Select.
3:2
1:0
Type
Bit
1. COBANK[1:0] and IFBANK[1:0] should not be set to select Bank 3 (11b) on the C8051F963/4/5 devices.
2. COBANK[1:0] and IFBANK[1:0] should not be set to select Bank 2 (10b) or Bank 3 (11b) on the
C8051F966/7/8 devices.
IFBANK[1:0] Instruction Fetch Operations Bank Select.
Reserved
Reserved
Name
R/W
7
0
Read = 00b, Must Write = 00b.
These bits select which flash bank is targeted during constant operations (MOVC
and flash MOVX) involving address 0x8000 to 0xFFFF.
00: Constant Operations Target Bank 0 (note that Bank 0 is also mapped between
0x0000 to 0x7FFF).
01: Constant operations target Bank 1.
10: Constant operations target Bank 2.
11: Constant operations target Bank 3.
Read = 00b, Must Write = 00b.
These bits select which flash bank is used for instruction fetches involving address
0x8000 to 0xFFFF. These bits can only be changed from code in Bank 0.
00: Instructions fetch from Bank 0 (note that Bank 0 is also mapped between
0x0000 to 0x7FFF).
01: Instructions fetch from Bank 1.
10: Instructions fetch from Bank 2.
11: Instructions fetch from Bank 3.
R/W
6
0
R/W
COBANK[1:0]
5
0
R/W
Rev. 0.5
4
0
Function
R/W
3
0
R/W
2
0
C8051F96x
R/W
1
0
IFBANK[1:0]
R/W
0
0
127
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