MAX11105AUT+TCBG Maxim Integrated, MAX11105AUT+TCBG Datasheet - Page 6

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MAX11105AUT+TCBG

Manufacturer Part Number
MAX11105AUT+TCBG
Description
Analog to Digital Converters - ADC SEL customer special of the MAX11105AUT+T
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX11105AUT+TCBG

Number Of Channels
1
Architecture
SAR
Conversion Rate
2 MSPs
Resolution
12 bit
Input Type
Single-Ended
Snr
73 dB
Interface Type
QSPI, SPI, Serial (3-Wire, Microwire)
Operating Supply Voltage
2.2 V to 3.6 V
Maximum Power Dissipation
696 mW
Number Of Converters
1
Voltage Reference
1 V
MAX11102/03/05/06/10/11/15/16/17
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11106)
(V
unless otherwise noted. Typical values are at T
ELECTRICAL CHARACTERISTICS (MAX11105) (continued)
(V
values are at T
6
Positive Supply Current (Full-
Power Mode), No Clock
Power-Down Current
Line Rejection
TIMING CHARACTERISTICS (Note 1)
Quiet Time
CS Pulse Width
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
Data Access Time After SCLK
Falling Edge
SCLK Pulse Width Low
SCLK Pulse Width High
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High-
Impedance
Power-Up Time
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unadjusted Error
Channel-to-Channel Offset
Matching
Channel-to-Channel Gain
Matching
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
DD
DD
= 2.2V to 3.6V, f
= 2.2V to 3.6V, V
PARAMETER
PARAMETER
A
= +25NC.)
SCLK
REF
= 32MHz, 50% duty cycle, 2Msps, C
= V
DD
, V
OVDD
SYMBOL
SYMBOL
SINAD
SFDR
I
DNL
SNR
THD
TUE
INL
VDD
I
OE
GE
t
PD
t
t
t
t
t
t
t
t
Q
1
2
3
4
5
6
7
8
= V
DD
A
, f
= +25NC.)
Leakage only
V
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Figure 2, V
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
Figure 3
Figure 4 (Note 2)
Conversion cycle (Note 2)
No missing codes
Excluding offset and reference errors
f
f
f
f
AIN_
AIN_
AIN_
AIN_
DD
SCLK
= +2.2V to +3.6V
= 1MHz
= 1MHz
= 1MHz
= 1MHz
= 48MHz, 50% duty cycle, 3Msps; C
DD
DOUT
= +2.2V to +3.6V
CONDITIONS
CONDITIONS
= 10pF, T
A
= -40NC to +125NC, unless otherwise noted. Typical
DOUT
MIN
MIN
2.5
10
40
40
10
61
61
75
4
5
1
5
= 10pF, T
Q0.05
Q0.05
Q0.5
Q0.5
TYP
1.48
TYP
61.8
61.8
1.3
0.7
-83
0
A
= -40NC to +125NC,
MAX
MAX
Q0.4
Q0.4
Maxim Integrated
-74
Q1
Q1
10
15
60
60
14
1
UNITS
UNITS
LSB/V
Cycle
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Bits
mA
FA
dB
dB
dB
dB
ns
ns
ns
ns
ns
ns
ns
%
%

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