MAX11105AUT+TCBG Maxim Integrated, MAX11105AUT+TCBG Datasheet - Page 14

• Manufacturer Part Number: MAX11105AUT+TCBG
• Description: Analog to Digital Converters - ADC SEL customer special of the MAX11105AUT+T
• Manufacturer: Maxim Integrated

Specifications of MAX11105AUT+TCBG

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 2 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: 73 dB
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Operating Supply Voltage: 2.2 V to 3.6 V
• Maximum Power Dissipation: 696 mW
• Number Of Converters: 1
• Voltage Reference: 1 V

MAX11102/03/05/06/10/11/15/16/17
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116) (continued)
(V
C
Note 1: All timing specifications given are with a 10pF capacitor.
Note 2: Guaranteed by design in characterization; not production tested.
14
Digital Input Low Voltage
Digital Input Hysteresis
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
Output High Voltage
Output Low Voltage
High-Impedance Leakage
Current
High-Impedance Output
Capacitance
POWER SUPPLY
Positive Supply Voltage
Positive Supply Current (Full-
Power Mode)
Positive Supply Current (Full-
Power Mode), No Clock
Power-Down Current
Line Rejection
TIMING CHARACTERISTICS (Note 1)
Quiet Time
CS Pulse Width
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
Data Access Time After SCLK
Falling Edge
SCLK Pulse Width Low
SCLK Pulse Width High
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High-
Impedance
Power-Up Time
DOUT
DD
= 2.2V to 3.6V. MAX11115: f
= 10pF, T
PARAMETER
A
= -40NC to +125NC, unless otherwise noted. Typical values are at T
SCLK
SYMBOL
V
C
I
I
V
V
V
HYST
C
I
VDD
VDD
I
V
OUT
I
t
OL
PD
OH
DD
t
t
t
t
t
t
t
t
= 32MHz, 50% duty cycle, 2Msps. MAX11116: f
OL
IL
Q
IN
1
2
3
4
5
6
7
8
IL
Inputs at GND or V
I
I
MAX11116, V
MAX11115, V
MAX11116
MAX11115
Leakage only
V
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Figure 2,
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
Figure 3
Figure 4 (Note 2)
Conversion cycle (Note 2)
SOURCE
SINK
DD
= +2.2V to +3.6V
= 200µA
= 200µA
V
DD
AIN
AIN
= +2.2V to +3.6V
CONDITIONS
= V
= V
DD
GND
GND
A
= +25NC.)
SCLK
0.85 x
V
= 48MHz, 50% duty cycle, 3Msps.
MIN
2.2
2.5
10
40
40
DD
4
5
1
5
0.001
TYP
0.15
V
1.98
1.48
0.17
1.3
DD
2
4
0.25 x
0.15 x
MAX
Q1.0
3.55
Maxim Integrated
V
V
3.6
2.6
Q1
10
15
60
60
14
DD
DD
1
UNITS
LSB/V
Cycle
mA
mA
FA
FA
FA
pF
pF
ns
ns
ns
ns
ns
ns
ns
%
%
V
V
V
V
V