MAX11105AUT+TCBG Maxim Integrated, MAX11105AUT+TCBG Datasheet - Page 24

• Manufacturer Part Number: MAX11105AUT+TCBG
• Description: Analog to Digital Converters - ADC SEL customer special of the MAX11105AUT+T
• Manufacturer: Maxim Integrated

Specifications of MAX11105AUT+TCBG

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 2 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: 73 dB
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Operating Supply Voltage: 2.2 V to 3.6 V
• Maximum Power Dissipation: 696 mW
• Number Of Converters: 1
• Voltage Reference: 1 V

MAX11102/03/05/06/10/11/15/16/17
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
To remain in normal mode, keep CS low until the falling
edge of the 10th SCLK cycle. Pulling CS high after the
10th SCLK falling edge keeps the part in normal mode.
However, pulling CS high before the 10th SCLK falling
24
Figure 8. Entering Power-Down Mode
Figure 9. Exiting Power-Down Mode
Figure 10. ADC Transfer Function
DOUT
SCLK
DOUT
SCLK
111...111
111...110
111...101
000...010
000...001
000...000
CS
CS
IMPEDANCE
OUTPUT CODE
IMPEDANCE
HIGH
HIGH
1
0
2
1
1
INVALID
3
2
DATA
4
3
2
5
INVALID DATA (DUMMY CONVERSION)
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE
6
7
3
8
FS - 1.5 x LSB
AIN1/AIN2 = REF (TDFN, µMax)
2
9
4
n
-2 2
INVALID DATA OR HIGH IMPEDANCE
10
FULL SCALE (FS):
n = RESOLUTION
AIN = V
n
-1 2
11
5
DD
n
12
(SOT)
13
ANALOG
INPUT (LSB)
6
14
15
7
16
IMPEDANCE
HIGH
N
8
edge terminates the conversion, DOUT goes into high-
impedance mode, and the device enters power-down
mode. See Figure 8.
In power-down mode, all bias circuitry is shut down
drawing typically only 1.3FA of leakage current. To save
power, put the device in power-down mode between
conversions. Using the power-down mode between
conversions is ideal for saving power when sampling the
analog input infrequently.
To enter power-down mode, drive CS high between the
2nd and 10th falling edges of SCLK (see Figure 8). By
pulling CS high, the current conversion terminates and
DOUT enters high impedance.
To exit power-down mode, implement one dummy con-
version by driving CS low for at least 10 clock cycles
(see Figure 9). The data on DOUT is invalid during this
dummy conversion. The first conversion following the
dummy cycle contains a valid conversion result.
The power-up time equals the duration of the dummy
cycle, and is dependent on the clock frequency. The
power-up time for 3Msps operation (48MHz SCLK) is
333ns. The power-up time for 2Msps operation (32MHz
SCLK) is 500ns.
1
9
2
3
10
4
5
11
6
7
VALID DATA
8
12
Entering Power-Down Mode
HIGH IMPEDANCE
9
Exiting Power-Down Mode
10
13
11
Power-Down Mode
12
14
13
Maxim Integrated
14
15
15
IMPEDANCE
16
HIGH
16