MAX11105AUT+TCBG Maxim Integrated, MAX11105AUT+TCBG Datasheet - Page 26

• Manufacturer Part Number: MAX11105AUT+TCBG
• Description: Analog to Digital Converters - ADC SEL customer special of the MAX11105AUT+T
• Manufacturer: Maxim Integrated

Specifications of MAX11105AUT+TCBG

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 2 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: 73 dB
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Operating Supply Voltage: 2.2 V to 3.6 V
• Maximum Power Dissipation: 696 mW
• Number Of Converters: 1
• Voltage Reference: 1 V

MAX11102/03/05/06/10/11/15/16/17
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
The MAX11102/MAX11103/MAX11106/MAX11111 fea-
ture dual-input channels. These devices use a channel-
select (CHSEL) input to select between analog input AIN1
(CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure
15, the CHSEL signal is required to change between the
2nd and 12th clock cycle within a regular conversion to
guarantee proper switching between channels.
The ICs can operate with 14 cycles per conversion.
Figure 16 shows the corresponding timing diagram.
Observe that DOUT does not go into high-impedance
mode. Also, observe that t
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for t
requirements and the Analog Input section for a descrip-
tion of the analog inputs.
Figure 15. Channel Select Timing Diagram
Figure 16. 14-Clock Cycle Operation
26
CHSEL
DOUT
SCLK
DOUT
SCLK
CS
CS
1
1
0
2
3
2
4
(MSB)
D11
14-Cycle Conversion Mode
5
Dual-Channel Operation
3
6
DATA CHANNEL AIN1
ACQ
D10
7
needs to be sufficiently
8
4
9
D9
10
5
11
D8
12
6
13
14
D7
ACQ
15
7
1/f
t
16
CONVERT
SAMPLE
D6
8
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
power supply, OVDD, and REF affects the ADC’s perfor-
mance. Bypass the V
0.1FF and 10FF bypass capacitors. Minimize capacitor
lead and trace lengths for best supply-noise rejection.
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
D5
1
9
2
D4
3
Layout, Grounding, and Bypassing
10
4
Applications Information
5
D3
DATA CHANNEL AIN2
6
Choosing an Input Amplifier
11
DD
7
, OVDD, and REF to ground with
D2
8
12
9
D1
10
11
13
12
D0
t
13
ACQ
Maxim Integrated
14
14
0
15
1
16
0
DD