S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 767
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S9S12G48F0MLH
Manufacturer Part Number
S9S12G48F0MLH
Description
16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G48F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G48F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
S9S12G48F0MLHR
Manufacturer:
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For the description of PACLK please refer
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
23.3.2.16 Pulse Accumulator Flag Register (PAFLG)
1
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while
clearing these bits.
Freescale Semiconductor
Module Base + 0x0021
.
Reset
W
R
0
0
7
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
PAMOD
CLK1
Unimplemented or Reserved
0
0
1
1
0
0
1
1
Figure 23-25. Pulse Accumulator Flag Register (PAFLG)
0
0
6
PEDGE
CLK0
MC9S12G Family Reference Manual, Rev.1.23
0
1
0
1
0
1
0
1
Table 23-20. Timer Clock Selection
0
0
5
Table 23-19. Pin Action
Use PACLK/65536 as timer counter clock frequency
Use PACLK/256 as timer counter clock frequency
Figure
Use timer prescaler clock as timer counter clock
Div. by 64 clock enabled with pin high level
Use PACLK as input to timer counter clock
Div. by 64 clock enabled with pin low level
NOTE
23-30.
0
0
4
Timer Clock
Falling edge
Rising edge
Pin Action
0
0
3
0
0
2
Timer Module (TIM16B8CV3)
PAOVF
0
1
PAIF
0
0
769
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