S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 209
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S9S12G48F0MLH
Manufacturer Part Number
S9S12G48F0MLH
Description
16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G48F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
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Price
Company:
Part Number:
S9S12G48F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
S9S12G48F0MLHR
Manufacturer:
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1
2.4.3.11
Freescale Semiconductor
Address 0x000C (G1)
Address 0x000C (G2, G3)
BKPUE
PDPEE
PUPDE
Read:Anytime in normal mode.
Write:Anytime, except BKPUE, which is writable in special mode only.
DDRE
Field
Field
Reset
Reset
1-0
6
4
3
W
W
R
R
Port E Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
BKGD pin Pullup Enable—Enable pullup device on pin
This bit configures whether a pullup device is activated, if the pin is used as input. If a pin is used as output this bit
has no effect. Out of reset the pullup device is enabled.
1 Pullup device enabled
0 Pullup device disabled
Port E Pulldown Enable—Enable pulldown devices on all port input pins
This bit configures whether a pulldown device is activated on all associated port input pins. If a pin is used as output
or used with the CPMU OSC function this bit has no effect. Out of reset the pulldown devices are enabled.
1 Pulldown devices enabled
0 Pulldown devices disabled
Port D Pullup Enable—Enable pullup devices on all port input pins
This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
1 Pullup devices enabled
0 Pullup devices disabled
Ports A, B, C, D, E, BKGD pin Pull Control Register (PUCR)
0
0
0
0
7
7
Figure 2-12. Ports A, B, C, D, E, BKGD pin Pullup Control Register (PUCR)
BKPUE
BKPUE
1
1
6
6
Table 2-31. DDRE Register Field Descriptions
Table 2-32. PUCR Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
0
0
0
0
5
5
PDPEE
PDPEE
1
1
4
4
Description
Description
PUPDE
3
0
3
0
0
PUPCE
0
0
0
2
2
Port Integration Module (S12GPIMV1)
PUPBE
Access: User read/write
Access: User read/write
0
0
0
1
1
PUPAE
0
0
0
0
0
211
1
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