S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 560
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S9S12G48F0MLH
Manufacturer Part Number
S9S12G48F0MLH
Description
16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G48F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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Analog-to-Digital Converter (ADC12B16CV2)
562
CD, CC,
CB, CA
MULT
Field
3–0
4
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0).
0 Sample only one channel
1 Sample across several channels
Analog Input Channel Select Code — These bits select the analog input channel(s).
coding used to select the various analog input channels.
In the case of single channel conversions (MULT=0), this selection code specifies the channel to be examined.
In the case of multiple channel conversions (MULT=1), this selection code specifies the first channel to be
examined in the conversion sequence. Subsequent channels are determined by incrementing the channel
selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel
Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by
WRAP3-0 the first wrap around will be AN16 to AN0.
SC
0
Table 16-14. ATDCTL5 Field Descriptions (continued)
CD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 16-15. Analog Input Channel Select Coding
MC9S12G Family Reference Manual,
CC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
CA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev.1.23
Analog Input
Channel
AN10
AN11
AN12
AN13
AN14
AN15
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
Freescale Semiconductor
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