S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 1253
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S9S12G48F0MLH
Manufacturer Part Number
S9S12G48F0MLH
Description
16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G48F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G48F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
S9S12G48F0MLHR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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0x0070–0x09F Analog to Digital Converter (ADC)
Freescale Semiconductor
Address
0x008A-
0x008C-
0x008E-
0x009A-
0x009C-
0x009E-
0x0080-
0x0082-
0x0084-
0x0086-
0x0088-
0x0090-
0x0092-
0x0094-
0x0096-
0x0098-
0x007C
0x007D
0x008D
0x009D
0x007A
0x007B
0x007E ATDCMPHTH
0x007F
0x0091
0x0083
0x0085
0x0087
0x0089
0x008B
0x008F
0x0091
0x0093
0x0095
0x0097
0x0099
0x009B
0x009F
ATDCMPHTL
ATDSTAT2H
ATDSTAT2L
ATDDIENH
ATDDIENL
ATDDR10
ATDDR11
ATDDR12
ATDDR13
ATDDR14
ATDDR15
ATDDR0
ATDDR1
ATDDR2
ATDDR3
ATDDR4
ATDDR5
ATDDR6
ATDDR7
ATDDR8
ATDDR9
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit 7
MC9S12G Family Reference Manual, Rev.1.23
Bit 6
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
See
See
See
See
See
See
See
See
See
See
See
See
See
See
See
See
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)”
Bit 5
Bit 4
CMPHT[15:8]
CMPHT[7:0]
CCF[15:8]
IEN[15:8]
CCF[7:0]
IEN[7:0]
Bit 3
Bit 2
Detailed Register Address Map
Bit 1
Bit 0
1255
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