SSTUAF32866BHLF IDT, Integrated Device Technology Inc, SSTUAF32866BHLF Datasheet - Page 7

• Manufacturer Part Number: SSTUAF32866BHLF
• Description: IC REGIST BUFF 25BIT DDR2 96-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUAF32866BHLF

• Logic Type: 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parity and Standby Function Table
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
RESET
1
2
C0 = 1.
3
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
H
H
H
H
H
H
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0.
Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1.
Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1.
PAR_IN arrives one clock cycle after the data to which it applies when C0 = 0, and two clock cycles when
This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
Floating
DCS
X or
H
X
X
X
X
X
L
L
L
L
Floating
CSR
X or
H
X
X
X
X
X
L
L
L
L
Floating
L or H
CLK
X or
↑
↑
↑
↑
↑
↑
↑
↑
↑
Inputs
Floating
L or H
CLK
X or
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
Σ of Inputs = H
7
X or Floating
(D1 - D25)
Even
Even
Even
Even
Odd
Odd
Odd
Odd
X
X
X or Floating
PAR_IN
COMMERCIAL TEMPERATURE GRADE
H
H
H
H
X
X
L
L
L
L
2
ICSSSTUAF32866B
PPO
PPO
PPO
H
H
H
H
L
L
L
L
L
0
0
Outputs
QERR
QERR
QERR
H
H
H
H
H
L
L
L
L
7096/13
0
0
3