IDT74SSTUBF32866BBFG8 IDT, Integrated Device Technology Inc, IDT74SSTUBF32866BBFG8 Datasheet

IDT74SSTUBF32866BBFG8

Manufacturer Part Number

IDT74SSTUBF32866BBFG8

Description

IC BUFFER 25BIT CONF DDR2 96BGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT74SSTUBF32866BBFG.pdf (30 pages)

Specifications of IDT74SSTUBF32866BBFG8

Logic Type

1:1, 1:2 Configurable Registered Buffer

Supply Voltage

1.7 V ~ 1.9 V

Number Of Bits

25, 14

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

96-BGA

Logic Family

SSTU

Logical Function

Registered Buffer

Number Of Elements

Number Of Inputs

Number Of Outputs

High Level Output Current

-8mA

Low Level Output Current

8mA

Propagation Delay Time

3ns

Operating Supply Voltage (typ)

1.8V

Operating Supply Voltage (max)

1.9V

Operating Supply Voltage (min)

1.7V

Clock-edge Trigger Type

Posit/Negat-Edge

Polarity

Non-Inverting

Technology

CMOS

Frequency (max)

410(Min)MHz

Mounting

Surface Mount

Pin Count

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74SSTUBF32866BBFG8

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUBF32866BBFG8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Current page: 1 of 30
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25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

designed for 1.7-V to 1.9-V V

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8-V CMOS drivers that have been optimized

to drive the DDR-II DIMM load. IDT74SSTUBF32866B

operates from a differential clock (CLK and CLK). Data are

registered at the crossing of CLK going high, and CLK

going low.

The C0 input controls the pinout configuration of the 1:2

pinout from A configuration (when low) to B configuration

(when high). The C1 input controls the pinout configuration

from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).

A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0,

C12 = 1)

Parity that arrives one cycle after the data input to which it

applies is checked on the PAR_IN of the first register. The

second register produces to PPO and QERR signals. The

QERR of the first register is left floating. The valid error

information is latched on the QERR output of the second

cycles or until RESET is low.

B - Single Configuration (C0 = 0, C1 = 0)

The device supports low-power standby operation. When

the RESET input (RESET) is low, the differential input

receivers are disabled, and undriven (floating) data, clock

and reference voltage (V

addition, when RESET is low all registers are reset, and all

outputs are forced low. The LVCMOS RESET and Cn inputs

must always be held at a valid logic high or low level. To

ensure defined outputs from the register before a stable

clock has been supplied, RESET must be held in the low

state during power up.

In the DDR-II RDIMM application, RESET is specified to be

completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be guaranteed

between the two. When entering reset, the register will be

cleared and the outputs will be driven low quickly, relative to

the time to disable the differential input receivers. However,

when coming out of reset, the register will become active

quickly, relative to the time to enable the differential input

receivers. As long as the data inputs are low, and the clock

is stable during the time from the low-to-high transition of

RESET until the input receivers are fully enabled, the

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

REF

) inputs are allowed. In

operation.

design of the IDT74SSTUBF32866B must ensure that the

outputs will remain low, thus ensuring no glitches on the

output.

The device monitors both DCS and CSR inputs and will

gate the Qn outputs from changing states when both DCS

and CSR inputs are high. If either DCS and CSR input is

low, the Qn outputs will function normally. The RESET input

has priority over the DCS and CSR control and will force the

outputs low. If the DCS-control functionality is not desired,

then the CSR input can be hardwired to ground, in which

case, the setup-time requirement for DCS would be the

same as for the other D data inputs. Package options

include 96-ball LFBGA (MO-205CC).

Features

•

Applications

•

25-bit 1:1 or 14-bit 1:2 registered buffer with parity check

functionality

Supports SSTL_18 JEDEC specification on data inputs

and outputs

Supports LVCMOS switching levels on C0, C1, and

RESET inputs

Low voltage operation: V

Available in 96-ball LFBGA package

DDR2 Memory Modules

Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

Ideal for DDR2 667 and 800

IDT74SSTUBF32866B

= 1.7V to 1.9V

IDT74SSTUBF32866B

DATASHEET

7067/13

Related parts for IDT74SSTUBF32866BBFG8

IDT74SSTUBF32866BBFG8 Summary of contents

Page 1

CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V operation. DD All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control ...

Page 2

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Functional Block Diagram for 1:1 Mode (Positive Logic) RESET CLK CLK V REF DCKE DODT DCS CSR D1 NOTE: 1. Disabled in 1:1 configuration. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ...

Page 3

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Functional Block Diagram for 1:2 Mode (Positive Logic) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS (D2-D6, D8-D10, D12-D13) NOTE: 1. Disabled in 1:1 configuration. 25-BIT CONFIGURABLE ...

Page 4

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Pin Configurations 14 BIT 1:2 REGISTERS DCKE PPO REF GND GND DODT GND GND ...

Page 5

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 96 Ball LFBGA Package Attributes Top Marking 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 C D ...

Page 6

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Function Table RESET DCS CSR ...

Page 7

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity and Standby Function Table RESET DCS CSR ...

Page 8

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Logic Diagram (1:1) G2 RESET H1 CLK J1 CLK D25 A3 REF PAR_IN G6 C0 Parity Logic Diagram for ...

Page 9

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Logic Diagram (1:2) G2 RESET H1 CLK J1 CLK D14 A3 REF PAR_IN G6 C0 Parity Logic Diagram for ...

Page 10

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Logic Diagram (1:2) G2 RESET H1 CLK J1 CLK D13 A3 REF PAR_IN G6 C0 Parity Logic Diagram for 1:2 Register - ...

Page 11

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...

Page 12

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Terminal Functions Terminal Name Characteristics GND REF CLK Differential Input CLK Differential Input C0, C1 RESET CSR, DCS D1 - D25 DODT DCKE Q1 - Q25 ...

Page 13

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Operating Characteristics The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is ...

Page 14

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter Output HIGH Voltage OH V Output LOW ...

Page 15

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Timing Requirements Over Recommended Operating Free-Air Temperature Range Symbol Parameter f Clock Frequency CLOCK t Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time ACT 2 t Differential ...

Page 16

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range Parameter dV/dt_r dV/dt_f 1 dV/dt_∆ 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 25-BIT CONFIGURABLE REGISTERED BUFFER ...

Page 17

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET DCS CSR CLK CLK t ACT ( D25 Q1 - Q25 (1) PARIN PPO (2) QERR Timing Diagram for SSTUBF32866B Used as a Single Device ...

Page 18

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing Timing Diagram for the First SSTUBF32866B Used as a Single Device RESET Held HIGH NOTE: 1.If the data is clocked in on the n clock ...

Page 19

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET (1) DCS (1) CSR (1) CLK (1) CLK ( D25 Q1 - Q25 (1) PARIN PPO QERR Timing Diagram for SSTUBF32866B Used as a Single Device ...

Page 20

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET DCS CSR CLK CLK t ACT ( D14 Q1 - Q14 (1) PARIN PPO (2) QERR (not used) Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) Device ...

Page 21

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) Device Used in a Pair RESET Held NOTE: 1.If the data is clocked in on the ...

Page 22

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET (1) DCS (1) CSR (1) CLK (1) CLK ( D14 Q1 - Q14 (1) PARIN PPO QERR (not used) Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) ...

Page 23

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET DCS CSR CLK CLK t ACT ( D14 Q1 - Q14 (1,2) PARIN PPO (not used) (3) QERR Timing Diagram for the Second SSTUBF32866B (1:2 Register-B Configuration) Device ...

Page 24

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing Timing Diagram for the Second SSTUBF32866B (1:2 Register-B Configuration) Device Used in a Pair RESET Held NOTES: 1.If the data is clocked in on the ...

Page 25

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET (1) DCS (1) CSR (1) CLK (1) CLK ( D14 Q1 - Q14 (1) PARIN PPO (not used) QERR Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) ...

Page 26

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT CLK Out CLK Inputs CLK Test Point R 100 L = Test Point Simulation Load Circuit LVCMOS RESET Input t ...

Page 27

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT Out Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% 20% dv_f dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out ...

Page 28

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT CLK CLK Output Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to clock inputs) LVCMOS RESET Input Output Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay ...

Page 29

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Ordering Information XX SSTUBF XX Family Temp. Range 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 XXX XX X Device Type Package Shipping Carrier 8 BFG 866B COMMERCIAL TEMPERATURE GRADE Tape and ...

Page 30

IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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