IDT74SSTVF16857PAG IDT, Integrated Device Technology Inc, IDT74SSTVF16857PAG Datasheet

IC BUFFER 14BIT SSTL I/O 48-TSSO

IDT74SSTVF16857PAG

Manufacturer Part Number
IDT74SSTVF16857PAG
Description
IC BUFFER 14BIT SSTL I/O 48-TSSO
Manufacturer
IDT, Integrated Device Technology Inc
Series
74SSTVFr
Datasheet

Specifications of IDT74SSTVF16857PAG

Logic Type
Registered Buffer with SSTL_2 Inputs and Outputs
Supply Voltage
2.3 V ~ 2.7 V
Number Of Bits
14
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74SSTVF16857PAG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT74SSTVF16857PAG
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT74SSTVF16857PAG
Quantity:
524
FEATURES:
• 2.3V to 2.7V Operation
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Drive up to equivalent of 14 SDRAM loads
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
• Available in TSSOP package
APPLICATIONS:
• Along with CSPT857C, Zero Delay PLL Clock buffer, provides
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT74SSTVF16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
c
complete solution for DDR1 DIMMs
machine model (C = 200pF, R = 0)
2003 Integrated Device Technology, Inc.
RESET
V
CLK
CLK
REF
D1
34
38
39
35
48
14-BIT REGISTERED
BUFFER WITH SSTL I/O
TO 13 OTHER CHANNELS
1
DESCRIPTION:
V
SSTL_2 level compatible with JEDEC standard for SSTL_2.
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of RESET.
DD
The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V
RESET is an LVCMOS input since it must operate predictably during the
RESET, when in the low state, will disable all input receivers, reset all
and supports low standby operation. All data inputs and outputs are
1D
R
C1
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16857
1
Q1
JUNE 2003
DSC-6198/8

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IDT74SSTVF16857PAG Summary of contents

Page 1

IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: • 2.3V to 2.7V Operation • SSTL_2 Class I style data inputs/outputs • Differential CLK input • RESET control compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Drive ...

Page 2

IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O PIN CONFIGURATION GND V 4 DDQ GND V 9 DDQ ...

Page 3

IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter V Control Inputs All ...

Page 4

IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE Symbol Parameter Clock Frequency CLOCK tw Pulse Duration, CLK, CLK HIGH or LOW t Differential Inputs Active Time (1) ACT t Differential Inputs Inactive Time ...

Page 5

IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O TEST CIRCUITS AND WAVEFORMS (V LVCMOS RESET Input t INACT I 10% DD (see note 2) Voltage and Current Waveforms Inputs Active and Inactive Times t W Input V REF ...

Page 6

IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O ORDERING INFORMATION XX XX IDT SSTV Temp. Range Family XXXX XX Device Type Package PA PAG 857 16 74 CORPORATE HEADQUARTERS San Jose, CA 95138 6 COMMERCIAL TEMPERATURE RANGE Thin Shrink Small Outline ...

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