IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 58

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
9. ELECTRICAL CHARACTERISTICS & AC TIMING
9.1 Timing Parameter by Speed Bin (DDR3-800, DDR3-1066)
Cycle to Cycle Period Jitter during DLL locking
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Clock Period Jitter during DLL locking period
Minimum Clock Cycle Time (DLL off mode)
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Absolute clock HIGH pulse width
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Absolute clock LOW pulse width
CL=10
CL=11
CL=12
CL=13
CL=9
Cycle to Cycle Period Jitter
Average high pulse width
Average low pulse width
Absolute Clock Period
Average Clock Period
Supported CWL Settings
Supported CL Settings
Clock Period Jitter
Duty Cycle Jitter
Clock Timing
Parameter
period
CWL=5,6,
CWL=5,6,
CWL =5
CWL =5
CWL =8
=5,6,7,8
CWL =9
CWL=8
CWL=6
CWL=7
CWL=8
CWL=6
CWL=7
CWL
7,8,9
7,8
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(DLL_OFF)
tERR(10per)
tERR(11per)
JIT(per, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
JIT(cc, lck)
tJIT(duty)
tCK(avg)
tCH(avg)
tCK(abs)
tCH(abs)
tCL(avg)
tCL(abs)
JIT(per)
Symbol
tJIT(cc)
5,6,7,8,9,10,11,12,13
1.07
1.5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5,6,7,8,9
<1.875
<1.25
DDR3/DDR3L-800
-100
-147
-175
-194
-209
-222
-232
-241
-249
-257
-263
Min.
0.47
0.47
0.43
0.43
200
180
-90
8
-
Max.: tCK(avg)max + tJIT(per)max
Min.: tCK(avg)min + tJIT(per)min
Refer to Standard Speed Bins
nCK
nCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
0.53
0.53
100
200
180
147
175
194
209
222
232
241
249
257
263
90
-
-
-
-
DDR3/DDR3L-1066
Min.
0.47
0.47
0.43
0.43
-132
-157
-175
-188
-200
-209
-217
-224
-231
-237
180
160
-90
-80
8
-
Max.
0.53
0.53
180
160
132
157
175
188
200
209
217
224
231
237
90
80
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
58
Notes
25
26
6