IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 20

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.4 DDR3 SDRAM Command Description and Operation
2.4.1 Command Truth Table
[BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don’t Care, V=Valid]
Notes:
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The MSB of BA, RA and CA
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
6.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self Refresh Exit is asynchronous.
9. VREF(Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. VrefDQ supply may be turned OFF and VREFDQ may take any
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Write with Auto Precharge (Fixed BL8
Read with Auto Precharge (Fixed BL8
Write with Auto Precharge (BC4, on
Read with Auto Precharge (BC4, on
Write with Auto Precharge (BL8, on
Read with Auto Precharge (BL8, on
are device density and configuration dependant.
value between VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first
Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh.
The Power Down Mode does not perform any refresh operation.
Read (Fixed BL8 or BC4)
Write (Fixed BL8 or BC4)
Single Bank Precharge
Write (BC4, on the Fly)
Read (BC4, on the Fly)
Read (BL8, on the Fly)
Write (BL8, on the Fly)
ZQ Calibration Short
Precharge all Banks
ZQ Calibration Long
Device Deselected
Mode Register Set
Power Down Entry
Self Refresh Entry
Power Down Exit
Self Refresh Exit
Bank Activate
No Operation
Function
Refresh
or BC4)
the Fly)
the Fly)
or BC4)
the Fly)
the Fly)
Abbrev
WRAS
WRAS
WRS4
WRS8
PREA
RDAS
RDAS
ZQCS
RDS4
RDS8
ZQCL
iation
WRA
MRS
SRE
SRX
PRE
RDA
NOP
DES
PDE
PDX
REF
ACT
WR
RD
4
8
4
8
Previo
Cycle
us
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
CKE
Curre
Cycle
nt
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CS
H
#
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RA
S#
X
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
X
H
X
H
H
L
L
L
CA
S#
X
H
H
H
H
H
H
H
H
H
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
WE
H
H
H
X
H
H
H
H
H
H
H
H
X
H
X
H
X
#
L
L
L
L
L
L
L
L
L
L
L
0-2
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
V
V
X
V
V
V
X
V
X
V
X
X
X
A11
A14
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
,A1
3,
V
V
X
V
V
V
V
X
V
X
V
X
X
X
Row Address(RA)
2/B
OP Code
C#
A1
V
V
X
V
H
H
H
H
V
V
V
L
V
L
V
L
V
L
V
X
V
X
V
X
X
X
0/A
A1
P
V
V
X
V
H
H
H
H
H
H
H
V
X
V
X
V
X
H
L
L
L
L
L
L
L
L
A0-
A9
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
V
V
X
V
V
V
V
X
V
X
V
X
X
X
20
7,9,1
7,8,9
Note
6,12
6,12
,12
10
11
s
2