ST72C334J4TAE STMicroelectronics, ST72C334J4TAE Datasheet - Page 99

• Manufacturer Part Number: ST72C334J4TAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces
• Manufacturer: STMicroelectronics

8-BIT A/D CONVERTER (ADC) (Cont’d)
13.6.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
to V
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (V
V
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
R
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
allotted time.
13.6.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in
■
■
While the ADC is on, these two phases are contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behavior is that it min-
imizes the current consumption on the analog pin
in case of single input channel measurement.
13.6.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in
tions and to
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/f
SSA
AIN
Sample capacitor loading [duration: t
During this phase, the V
measured is loaded into the C
capacitor.
A/D conversion [duration: t
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the C
from the analog input pin to get the optimum
analog to digital conversion accuracy.
DDA
is the maximum recommended impedance
(low-level voltage reference) then the con-
(high-level voltage reference) then the
ADC
Figure 51
sample capacitor is disconnected
Section 13.6.6
ADC
AIN
Figure
= 2/f
AIN
) is lower than or equal to
for the timings.
) is greater than or equal
CPU
AIN
51:
CONV
).
input voltage to be
for the bit defini-
]
ADC
LOAD
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
sample
]
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the
PORTS
puts does not affect the ability of the port to be
read as a logic input.
In the CSR register:
ADC Conversion
In the CSR register:
When a conversion is complete
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 51. ADC Conversion Timings
13.6.4 Low Power Modes
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
13.6.5 Interrupts
None
ADON
HOLD
CONTROL
– Select the CH[3:0] bits to assign the analog
– Set the ADON bit to enable the A/D converter
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
Mode
WAIT
HALT
channel to be converted.
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
valid until the next conversion has ended.
t
LOAD
chapter. Using these pins as analog in-
No effect on A/D Converter
A/D Converter disabled.
After wake-up from Halt mode, the A/D Con-
verter requires a stabilization time before ac-
curate conversions can be performed.
t
CONV
COCO BIT SET
Description
ADCCSR WRITE
OPERATION
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I/O