ST72C334J4TAE STMicroelectronics, ST72C334J4TAE Datasheet - Page 73

• Manufacturer Part Number: ST72C334J4TAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces
• Manufacturer: STMicroelectronics

13.4 SERIAL PERIPHERAL INTERFACE (SPI)
13.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
Refer to the
device-specific pinout.
13.4.2 Main Features
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Figure 41. Serial Peripheral Interface Master/Slave
Full duplex, three-wire synchronous transfers
Master or slave operation
4 master mode frequencies
Maximum slave mode frequency = f
4 programmable master bit rates
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision flag protection
Master mode fault protection capability
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
PIN DESCRIPTION
MASTER
LSBit
chapter for the
CPU
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
/4
SCK
MOSI
SS
MISO
+5V
13.4.3 General description
The SPI is connected to external devices through
four alternate pins:
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see
must be programmed with the same timing mode.
MOSI
MISO
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
SCK
SS
41.
Figure
8-BIT SHIFT REGISTER
MSBit
44) but master and slave
SLAVE
LSBit
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