MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 74

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MT46V64M16P-6T IT:A

Manufacturer Part Number
MT46V64M16P-6T IT:A
Description
DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
Manufacturer
Micron
Datasheet
Figure 46:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Command
BA0, BA1
Address
DQS
DQ 5
CK#
CKE
A10
DM
CK
t
t
IS
IS
NOP 1
Bank WRITE – Without Auto Precharge
T0
t
t
IH
IH
Notes:
t
t
Bank x
IS
IS
Row
Row
ACT
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 48 on page 76 for detailed DQ timing.
t
t
IH
IH
t
times.
CK
t
t
RCD
RAS
NOP 1
T2
t
CH
t
CL
WRITE 2
t
Bank x
Col n
IS
3
T3
t
t
DQSS (NOM)
IH
t
WPRES
t DS
74
t
WPRE
NOP 1
T4
DI
b
t DH
T4n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSL
NOP 1
T5
t
DQSH
1Gb: x4, x8, x16 DDR SDRAM
T5n
t
WPST
NOP 1
T6
Transitioning Data
©2000 Micron Technology, Inc. All rights reserved.
t
NOP 1
WR
T7
Operations
One bank
All banks
Don’t Care
Bank x 4
T8
PRE
t
RP

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