MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 59

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

Figure 31:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Command
Command
Command
Address
Address
Address
READ-to-PRECHARGE
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
Notes:
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
CL = 2
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
RAS (MIN) is met.
CL = 3
t
AC,
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
PRE
T2
PRE
PRE
T2
T2
t
DQSCK, and
59
DO
n
T2n
T2n
DO
n
T3
NOP
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NOP
NOP
T3
T3
t
DQSQ.
DO
n
t RP
t RP
t RP
T3n
T3n
T3n
Transitioning Data
1Gb: x4, x8, x16 DDR SDRAM
T4
T4
T4
NOP
NOP
NOP
t
RC (MIN) is met.
T4n
©2000 Micron Technology, Inc. All rights reserved.
Bank a,
Bank a,
Bank a,
T5
T5
T5
ACT
Row
Row
Row
ACT
ACT
Don’t Care
Operations