CY7C4292V-15ASCT Cypress Semiconductor, CY7C4292V-15ASCT Datasheet - Page 6

• Manufacturer Part Number: CY7C4292V-15ASCT
• Manufacturer: Cypress Semiconductor

Document #: 38-06014 Rev. *B
Depth Expansion Configuration
The CY7C4282V/92V can easily be adapted to applications
requiring more than 64K/128K words of buffering. Figure 3
shows Depth Expansion using three CY7C4282V/92Vs.
Maximum depth is limited only by signal loading. Follow these
steps:
1. The first device must be designated by grounding the First
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
4. EF and FF composite flags are created by ORing together
Load (FL) control input.
the Expansion In (XI) pin of the next device.
each individual respective flag.
DATA IN (D)
Figure 3. Block Diagram of 64Kx9/128Kx9 Low-Voltage Deep Sync FIFO Memory
FF
WRITECLOCK (WCLK)
WRITEENABLE (WEN)
RESET (RS)
with Programmable Flags used in Depth Expansion Configuration
FIRST LOAD (FL)
V
V
CC
CC
D
D
WEN
WCLK
WEN
RS
WCLK
RS
D
FL
WCLK
WEN
RS
FF
FF
FF
FL
FL
7C4282V
7C4292V
7C4282V
7C4292V
7C4282V
7C4292V
XO
XO
XO
XI
XI
XI
RCLK
RCLK
REN
RCLK
REN
OE
REN
OE
OE
EF
EF
EF
Q
Q
Q
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUTENABLE (OE)
EF
DATA OUT (Q)
CY7C4282V
CY7C4292V
Page 6 of 15
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