CY7C4292V-15ASCT Cypress Semiconductor, CY7C4292V-15ASCT Datasheet - Page 12

• Manufacturer Part Number: CY7C4292V-15ASCT
• Manufacturer: Cypress Semiconductor

Document #: 38-06014 Rev. *B
Switching Waveforms
Notes:
21. t
22. PAE offset= n.
23. If a read is performed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW
24. If a write is performed on this rising edge of the write clock, there will be Full
25. 64K
26. t
Programmable Almost Empty Flag Timing
Programmable Almost Full Flag Timing
RCLK is less than t
the rising edge of WCLK is less than t
SKEW2
SKEW2
REN
RCLK
WCLK
WEN
PAE
WCLK
WEN
REN
RCLK
m words for CY7C4282V, 128K
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
PAF
t
SKEW2
CLKH
t
CLKH
, then PAE may not change state until the next RCLK.
(continued)
FULL
SKEW2
t
SKEW2
, then PAF may not change state until the next WCLK.
m words for CY4292V.
(M+1)WORDS
IN FIFO
t
[21]
ENS
t
ENS
t
ENH
t
ENH
t
CLKL
t
CLKL
Note
22
t
PAE
Note
24
(m 1) words of the FIFO when PAF goes LOW.
t
PAF
t
t
ENS
ENS
t
SKEW2
FULL
N + 1 WORDS
IN FIFO
IN FIFO
t
t
ENS
ENS
[26]
M WORDS
t
[25]
t
ENH
ENH
CY7C4282V
CY7C4292V
Note
t
PAF
23
Page 12 of 15
t
PAE
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