CY7C4292V-15ASCT Cypress Semiconductor, CY7C4292V-15ASCT Datasheet - Page 2

• Manufacturer Part Number: CY7C4292V-15ASCT
• Manufacturer: Cypress Semiconductor

Document #: 38-06014 Rev. *B
Selection Guide
Pin Definitions
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current (I
Density
Package
D
Q
WEN
REN
WCLK
RCLK
EF
Pin Configuration
Signal Name
0 8
0 8
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Empty Flag
Description
64k × 9
64-pin 10 × 10 TQFP
CC
WEN
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RS
D
D
D
D
D
D
D
) Commercial
8
7
6
5
4
3
2
I/O
Industrial
O Data Outputs for 9-bit bus.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
I
I
I
I
I
Data Inputs for 9-bit bus.
The only write enable when device is configured to have programmable flags. Data
is written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
Enables the device for Read operation. REN must be asserted LOW to allow a Read
operation.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is LOW, RCLK reads data out of the programmable flag-offset register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4282V
CY7C4282V
CY7C4292V
7C4282V/92V-10
Top View
STQFP
100
3.5
10
25
8
0
8
Description
7C4282V/92V-15
128k × 9
64-pin 10 × 10 TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
66.7
10
15
10
25
30
4
0
Q
Q
GND
Q
Q
V
Q
Q
GND
N/C
FF
EF
OE
GND
FL/RT
N/C
CC
5
4
3
2
1
0
CY7C4292V
7C4282V/92V-25
CY7C4282V
CY7C4292V
40
15
25
15
25
6
1
Page 2 of 15
MHz
Unit
mA
ns
ns
ns
ns
ns
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