CY7C4292V-15ASCT Cypress Semiconductor, CY7C4292V-15ASCT Datasheet - Page 10

• Manufacturer Part Number: CY7C4292V-15ASCT
• Manufacturer: Cypress Semiconductor

Document #: 38-06014 Rev. *B
Switching Waveforms
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. For standalone or width expansion configuration only.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
19. When t
20. The first word is available the cycle after EF goes HIGH, always.
REN, WEN
First Data Word Latency after Reset with Simultaneous Read and Write
Reset Timing
Q
D
Q
0
0
EF,PAE
FF,PAF
WCLK
The Latency Timing applies only at the Empty Boundary (EF = LOW).
RCLK
WEN
0 –
–D
–Q
REN
OE
RS
EF
LD
Q
8
8
8
[17]
SKEW1
t
ENS
> minimum specification, t
[16]
t
DS
D
0
(FIRSTVALID WRITE)
(continued)
FRL
(maximum) = t
t
SKEW1
t
t
t
t
RSS
RSF
RSF
RSF
t
RS
t
OLZ
t
FRL
CLK
[19]
+ t
SKEW2
t
. When t
REF
D
1
SKEW1
t
< minimum specification, t
OE
t
RSR
t
D
A
2
FRL
(maximum) = either 2*t
D
0
t
A
[20]
D
3
CLK
CY7C4282V
CY7C4292V
+ t
OE=1
OE=0
SKEW1
[18]
Page 10 of 15
or t
CLK
D
+ t
1
D
SKEW1
4
.
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