E28F320J5100 Intel, E28F320J5100 Datasheet - Page 7

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

A
A
DQ
DQ
CE
CE
CE
RP#
OE#
WE#
STS
0
1
PRELIMINARY
Symbol
–A
0
1
2
0
8
,
,
–DQ
–DQ
22
7
15
OUTPUT
OUTPUT
OUTPUT
INPUT/
INPUT/
DRAIN
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OPEN
Type
BYTE-SELECT ADDRESS: Selects between high and low byte when the device
is in x8 mode. This address is latched during a x8 program cycle. Not used in
x16 mode (i.e., the A
ADDRESS INPUTS: Inputs for addresses during read and program operations.
Addresses are internally latched during a program cycle.
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and
inputs commands during Command User Interface (CUI) writes. Outputs array,
query, identifier, or status data in the appropriate read mode. Floated when the
chip is de-selected or the outputs are disabled. Outputs DQ
floated when the Write State Machine (WSM) is busy. Check SR.7 (Status
Register bit 7) to determine WSM status.
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming
operations. Outputs array, query, or identifier data in the appropriate read mode;
not used for Status Register reads. Floated when the chip is de-selected, the
outputs are disabled, or the WSM is busy.
CHIP ENABLES: Activates the device’s control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected (see Table 2, Chip Enable
Truth Table ), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection
occurs with the first edge of CE
deselection occurs with the first edge of CE
device (see Table 2, Chip Enable Truth Table ).
RESET/ POWER-DOWN: Resets internal automation and puts the device in
power-down mode. RP#-high enables normal operation. Exit from reset sets the
device to read array mode. When driven low, RP# inhibits write operations which
provides data protection during power transitions.
RP# at V
when the master lock-bit is set. RP# = V
enabling block erase and programming operations to locked memory blocks. Do
not permanently connect RP# to V
OUTPUT ENABLE: Activates the device’s outputs through the data buffers
during a read cycle. OE# is active low.
WRITE ENABLE: Controls writes to the Command User Interface, the Write
Buffer, and array blocks. WE# is active low. Addresses and data are latched on
the rising edge of the WE# pulse.
STATUS: Indicates the status of the internal state machine. When configured in
level mode (default mode), it acts as a RY/BY# pin. When configured in one of
its pulse modes, it can pulse to indicate program and/or erase completion. For
alternate configurations of the STATUS pin, see the Configurations command.
Tie STS to V
32-Mbit: A
64-Mbit: A
INTEL
HH
enables master lock-bit setting and block lock-bits configuration
®
CCQ
Table 1. Lead Descriptions
0
0
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
–A
–A
21
22
with a pull-up resistor.
0
input buffer is turned off when BYTE# is high).
Name and Function
0
, CE
HH
1
.
, or CE
HH
overrides block lock-bits thereby
0
, CE
2
that enables the device. Device
1
, or CE
2
that disables the
6
–DQ
0
are also
7