E28F320J5100 Intel, E28F320J5100 Datasheet - Page 48

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
6.6
NOTES:
CE
CE
1.
2.
3.
4.
5.
6.
7.
8.
9.
48
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
X
1
, or CE
#
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations .
A write operation can be initiated and terminated with either CE
Sampled, not 100% tested.
Refer to Table 4 for valid A
STS timings are based on STS configured in its RY/BY# default mode.
For array access, t
V
lock-bit configuration success (SR.1/3/4/5 = 0).
Write pulse width (t
(whichever goes high first). Hence, t
WE# pulse width requirement decreases to t
Write pulse width high (t
(whichever goes low first). Hence, t
low is defined as the first edge of CE
PEN
®
should be held at V
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC Characteristics— Write Operations
PHWL
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
WPH
PHHWH
VPWH
WHGL
WHRL
QVPH
QVVL
2
that disables the device (see Table 2, Chip Enable Truth Table ).
Sym
( t
(t
( t
( t
( t
( t
( t
( t
( t
( t
WLEL
PHEL
( t
EHRL
DVEH
AVEH
EHWH
EHDX
EHAX
VPEH
EHGL
PHHEH
AVQV
WP
)
)
)
)
)
)
)
)
)
)
) is defined from CE
)
is required in addition to t
WPH
PENH
IN
RP# High Recovery to WE# (CE
Low
CE
Write Pulse Width
Data Setup to WE# (CE
Address Setup to WE# (CE
CE
Data Hold from WE# (CE
Address Hold from WE# (CE
Write Pulse Width High
RP# V
V
Write Recovery before Read
WE# (CE
RP# V
High
V
) is defined from CE
PEN
PEN
and D
(and if necessary RP# should be held at V
X
X
(WE#) Low to WE# (CE
(WE#) Hold from WE# (CE
Setup to WE# (CE
Hold from Valid SRD, STS Going High
HH
HH
IN
WPH
WP
0
for block erase, program, or lock-bit configuration.
, CE
X
Versions
Setup to WE# (CE
Hold from Valid SRD, STS Going
= t
) High to STS Going Low
= t
X
WLWH
WHWL
1
, or CE
or WE# going low (whichever goes low first) to CE
WP
Parameter
= t
- 10 ns.
X
= t
WHGL
or WE# going high (whichever goes high first) to CE
ELEH
2
EHEL
that enables the device. CE
for any accesses after a write.
X
X
= t
= t
) Going High
X
) Going High
WLEH
) High
WHEL
X
X
X
) Going High
X
) Going Low
) Going High
) High
X
= t
= t
X
) High
X
or WE#.
(1,2)
ELWH
EHWL
) Going
. If CE
.
HH
) until determination of block erase, program, or
X
is driven low 10 ns before WE# going low,
X
high is defined at the first edge of CE
Notes
3,5,7
3,5,7
3
8
8
4
4
9
3
3
6
5
PRELIMINARY
X
Valid for All
Min
70
50
50
10
30
35
or WE# going high
1
0
0
0
0
0
0
0
Speeds
X
or WE# going low
Max
90
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
,