E28F320J5100 Intel, E28F320J5100 Datasheet - Page 32

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
32
High Z
Busy?
When
Yes
Yes
Yes
Yes
Yes
Yes
Yes
WSMS
No
bit 7
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
SR.7 = WRITE STATE MACHINE STATUS
SR.6 = ERASE SUSPEND STATUS
SR.5 = ERASE AND CLEAR LOCK-BITS
SR.4 = PROGRAM AND SET LOCK-BIT STATUS
SR.3 = PROGRAMMING VOLTAGE STATUS
SR.2 = RESERVED FOR FUTURE
SR.1 = DEVICE PROTECT STATUS
SR.0 = RESERVED FOR FUTURE
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
1 = Error in Programming or Set Master/Block
0 = Successful Programming or Set
1 = Low Programming Voltage Detected,
0 = Programming Voltage OK
1 = Master Lock-Bit, Block Lock-Bit and/or
0 = Unlock
bit 6
ESS
STATUS
Lock-Bit
Master/Block Lock Bit
Operation Aborted
ENHANCEMENTS
RP# Lock Detected, Operation Abort
ENHANCEMENTS
Status Register Bits
ECLBS
bit 5
Table 16. Status Register Definitions
PSLBS
bit 4
VPENS
bit 3
Check STS or SR.7 to determine block
erase, program, or lock-bit configuration
completion. SR.6–SR.0 are not driven while
SR.7 = “0.”
If both SR.5 and SR.4 are “1”s after a block
erase or lock-bit configuration attempt, an
improper command sequence was entered.
SR.3 does not provide a continuous
programming voltage level indication. The
WSM interrogates and indicates the
programming voltage level only after Block
Erase, Program, Set Block/Master Lock-Bit,
or Clear Block Lock-Bits command
sequences.
SR.1 does not provide a continuous
indication of master and block lock-bit
values. The WSM interrogates the master
lock-bit, block lock-bit, and RP# only after
Block Erase, Program, or Lock-Bit
configuration command sequences. It
informs the system, depending on the
attempted operation, if the block lock-bit is
set, master lock-bit is set, and/or RP# is not
V
configuration codes using the Read
Identifier Codes command to determine
master and block lock-bit status.
SR.2 and SR.0 are reserved for future use
and should be masked when polling the
status register.
HH
. Read the block lock and master lock
bit 2
R
NOTES:
PRELIMINARY
DPS
bit 1
bit 0
R