E28F320J5100 Intel, E28F320J5100 Datasheet - Page 17

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If the block is locked, RP# must be at V
11. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
12. If the master lock-bit is set, RP# must be at V
13. If the master lock-bit is set, RP# must be at V
14. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
15. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
PRELIMINARY
Bus operations are defined in Table 3.
X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 6 and Table 13.
QA = Query database Address.
PA = Address of memory location to be programmed.
ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See Table 16 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.
The upper byte of the data bus (DQ
Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Read Identifier Codes Command section for read identifier code data.
If the WSM is running, only DQ
After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges
on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and
consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is
expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer
operation. Please see Figure 7, Write to Buffer Flowchart , for additional information.
Programming the write buffer to flash or initiating the erase operation does not begin until a confirm command (D0h) is
issued.
program to a locked block while RP# is V
master lock-bit is not set, a block lock-bit can be set while RP# is V
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
7
is valid; DQ
INTEL
8
–DQ
HH
15
IH
®
to enable block erase or program operations. Attempts to issue a block erase or
) during command writes is a “Don’t Care” in x16 operation.
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
will fail.
15
HH
HH
–DQ
to set a block lock-bit. RP# must be at V
to clear block lock-bits. The clear block lock-bits operation simultaneously
8
and DQ
6
–DQ
0
IH
float, which places them in a high-impedance state.
.
HH
to set the master lock-bit. If the
17
IH
.